Data conversion for data acquisition is a two-part process that involves sampling and then converting signals into digital venues. These processes inherently remove part of the complete analog signal in exchange for the power and robustness of digital signal handling. This becomes especially difficult when trying to capture signals at the limits of the resolution and speed of our systems. In this session, learn how to design a data conversion system that minimizes the signal loss to match the signal handling requirements … even on the hard ones.
3. Today’s Agenda
Data converters in the signal chain
Basics of data conversion
Dynamic signal processing
Driving ADCs
Input structures
DACs for high speed and high resolution
3
4. Analog to Electronic Signal Processing
4
SENSOR
(INPUT)
DIGITAL
PROCESSOR
AMP CONVERTER
ACTUATOR
(OUTPUT)
AMP CONVERTER
5. Analog to Electronic Signal Processing
5
SENSOR
(INPUT)
DIGITAL
PROCESSOR
AMP ADC
ACTUATOR
(OUTPUT)
AMP DAC
6. Analog and Digital Domains
Why Convert to Digital?
6
Analog signals are continuous and provide the entire signal
Digital signals capture only a portion of the signal
Why digitize?
Improved signal analysis potential
More robust storage
More accurate transmission
Why not digitize?
Cost
Complexity
Processing time available.
Development objective of sampled data systems is to minimize
effect of the sampling process
7. Basic ADC with External Reference
7
VDD
VSS
GROUND
(MAY BE INTERNALLY
CONNECTED TO VSS)
ANALOG
INPUT
VREF
DIGITAL
OUTPUT
SAMPLING
CLOCK
CONTROL SIGNALS
(EOC, DATA READY, ETC.)
ADC
VDIO
8. Sampled Data System: Sampling and
Quantization
8
LPF
OR
BPF
N-BIT
ADC
DSP
N-BIT
DAC
LPF
OR
BPF
fa
fs fs
t
AMPLITUDE
QUANTIZATION DISCRETE
TIME SAMPLING
fa
1
fs
ts=
11. The Size of a Least Significant Bit (LSB)
11
VOLTAGE
(10V FS)
2.5 V
625 mV
156 mV
39.1 mV
9.77 mV (10 mV)
2.44 mV
610 mV
153 mV
38 mV
9.54 mV (10 mV)
2.38 mV
596 nV*
ppm FS
250,000
62,500
15,625
3,906
977
244
61
15
4
1
0.24
0.06
% FS
25
6.25
1.56
0.39
0.098
0.024
0.0061
0.0015
0.0004
0.0001
0.000024
0.000006
dB FS
-12
-24
-36
-48
-60
-72
-84
-96
-108
-120
-132
-144
RESOLUTION
N
2-bit
4-bit
6-bit
8-bit
10-bit
12-bit
14-bit
16-bit
18-bit
20-bit
22-bit
24-bit
2N
4
16
64
256
1,024
4,096
16,384
65,536
262,144
1,048,576
4,194,304
16,777,216
*600nV is the Johnson Noise in a 10kHz BW of a 2.2kW Resistor @ 25°C
12. Practical Resolution Needs for Data Converters
Instrumentation measurements
Sensor resolution/accuracy of 0.5% = 1/200
8 bits equivalent to 1/256 -- digitizing will lose information
10x sensor resolution = 1/2000 -- 12 bits is 1/4096
Allows discrimination of small changes
Can also be driven by display requirements
Dynamic signal measurements
Audio systems need better than 0.1% distortion at 5% of full scale
Equivalent to 1/20,000 -- 16 bits is 1/65,536
12
13. Transfer Functions for Ideal 3-Bit DAC and ADC
13
DIGITAL INPUT
ANALOG
OUTPUT
FS
000 001 010 011 100 101 110 111 ANALOG INPUT
DIGITAL
OUTPUT
FS
000
001
010
011
100
101
110
111
QUANTIZATION
UNCERTAINTY
QUANTIZATION
UNCERTAINTY
DAC ADC
14. Primary Errors in Data Converters
(DC Parametrics)
Instrumentation and measurement
Described in LSBs (least-significant-bit), % of FS, ppm of FS
Offset error – the input level needed to change the first code
Gain/full-scale error – the input level need to change the last code
Nonlinearity – deviation of codes from the line from zero to FS
Differential nonlinearity – code-to-code deviation from 1 LSB
Transition noise – ADC uncertainty in code center point
14
15. Primary Errors in Data Converters
(AC Parametrics)
15
Dynamic systems
SINAD (Signal-to-Noise-and-Distortion Ratio):
The ratio of the rms signal amplitude to the mean value of the root-
sum-squares (RSS) of all other spectral components, including
harmonics, but excluding DC.
ENOB (Effective Number of Bits):
SNR (Signal-to-Noise Ratio), or Signal-to-Noise Ratio without
Harmonics:
The ratio of the rms signal amplitude to the mean value of the root-
sum-squares (RSS) of all other spectral components, excluding the first
5 harmonics and DC
SFDR (Spurious-Free-Dynamic-Range) Signal dynamic range in the
bandwidth of interest containing no frequency noise spurs
ENOB =
SINAD – 1.76dB
6.02dB
16. Quantifying Data Converter
Dynamic Performance
16
Harmonic Distortion
Worst Harmonic
Total Harmonic Distortion (THD)
Total Harmonic Distortion Plus Noise (THD + N)
Signal-to-Noise-and-Distortion Ratio (SINAD, or S/N +D)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Analog Bandwidth (Full-Power, Small-Signal)
Spurious Free Dynamic Range (SFDR)
Two-Tone Intermodulation Distortion
Multi-tone Intermodulation Distortion
Noise Power Ratio (NPR)
Adjacent Channel Leakage Ratio (ACLR)
Noise Figure
Settling Time, Overvoltage Recovery Time
17. The Comparator: A 1-Bit ADC
17
DIFFERENTIAL
ANALOG INPUT
LOGIC
OUTPUT
LATCH
ENABLE
DIFFERENTIAL ANALOG INPUT
COMPARATOR
OUTPUT
"0"
"1"
0
VHYSTERESIS
+
–
18. Quantization and Quantization Noise
18
001
010
011
100
101
110
111
1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS
NORMALIZED ANALOG INPUT
DIGITALOUTPUT
Quantization noise error: RMS value is LSB/3.464
Quantization
error function
19. Combined Effects of Code Transition Noise
and DNL
19
ADC INPUT ADC INPUT ADC INPUT
CODE TRANSITION NOISE DNL TRANSITION NOISE
AND DNL
ADC
OUTPUT
CODE
22. Nyquist's Criteria
A signal with a maximum bandwidth of fa must be sampled at a rate fs > 2fa
or information about the signal will be lost because of aliasing.
Aliasing occurs whenever fs < 2fa
A signal which has frequency components between fa and fb must be
sampled at a rate fs > 2 (fb – fa) in order to prevent alias components from
overlapping the signal frequencies.
The concept of aliasing is widely used in communications applications
such as direct IF-to-digital conversion.
22
23. Analog Signal fa Sampled @ fs Has Images
(Aliases) At |±Kfs ±fa|, K = 1, 2 ...
23
0.5fs
0.5fs
fs
fs
1.5fs
1.5fs
2fs
2fs
ZONE 1 ZONE 2 ZONE 3 ZONE 4
fa I I I
I III
I
fa
24. Oversampling Relaxes Requirements
on Baseband Antialiasing Filter
24
BA
DR
fs
fa fs– fa
Kfs – f
a
fa
fs
2
KfsKfs
2
STOPBAND ATTENUATION = DR
TRANSITION BAND: fa to fs – fa
CORNER FREQUENCY: fa
STOPBAND ATTENUATION = DR
TRANSITION BAND: fa to Kfs – fa
CORNER FREQUENCY: fa
25. Advantages of Differential Analog Input
Interfaces for Data Converters
Differential inputs give twice the signal swing vs. single-ended
(especially important for low voltage single-supply operation)
Differential inputs help suppress even order distortion products
Many IF/RF components such as SAW filters and mixers are
differential
Differential inputs suppress common-mode ADC switching noise
including LO feed-through from mixer and filter stages
Differential ADC designs allow better internal component matching
and tracking than single-ended. Less need for trimming
Helps minimize the effects of noise on the ground.
If you drive them single-ended, you will have degradation in
distortion and noise performance
However, many signal sources are single-ended, so the differential
amplifier is useful as a single-ended to differential converter
2.25
29. Input Impedance Model for Buffered and
Unbuffered Input ADCs
2.29
R C
ADC
ZIN
BUFFERED INPUT
R and C are constant over frequency
Typically:
R: 1 kW – 2 kW
C: 1.5 pF – 3 pF
UNBUFFERED INPUT
R and C vary with both frequency and mode
(track/hold)
Use Track mode R and C at the input frequency
of interest
30. 2.30
Unbuffered CMOS ADC (AD9236 12-Bit, 80 MSPS)
Series Input Impedance in Track Mode and Hold Mode
REAL Z, HOLD
REAL Z, TRACK
IMAG Z, TRACK
IMAG Z, HOLD
ANALOG INPUT FREQUENCY (MHz)
SERIESREALIMPEDANCE(OHMS)
SERIESIMAGINARYIMPEDANCE(pF)
200
180
160
140
120
100
80
60
40
20
0
20
18
16
14
12
10
8
6
4
2
0
0 100 200 300 400 500 600 700 800 900 1000
RSZIN
CS
31. Basic Principles of Resonant Matching
2.31
(2 f )2 CS
RSZIN
CS
RP
ZIN
CP
LS/2
LS/2
LP
LS =
1
(2 f )2 CP
LP =
1
SERIES RESONANT @ f (70MHz) PARALLEL RESONANT @ f (70MHz)
ZIN = RS + j0 @ f ZIN = RP + j0 @ f
ADC ADC
Make XLS = XCS Make XLP = XCP
f
|ZIN|
RP
|ZIN|
RS
f
4kW @ 70MHz
For AD9236
69W @ 70MHz
For AD9236
(69W)
(4.3pF)
(4kW) (4.3pF)
(1.2µH) (1.2µH)
32. Before and After Adding
Matching Analog Antialiasing Filter Network
2.32
SFDR Improved by 13.4 dB, SNR improved by 10.7 dB
Note: Measured at maximum gain of 35 dB (gain code 255, high gain mode) using
76.8 MHz sampling clock
SAMPLING RATE = 76.8MSPS
INPUT = 70MHz
NOISE FLOOR = –84.3dBFS
THD = –63.9dBc
SFDR = 68.0dBc
SNR = 42.1dBFS
SAMPLING RATE = 76.8MSPS
INPUT = 70MHz
NOISE FLOOR = –84.3dBFS
THD = –63.9dBc
SFDR = 68.0dBc
SNR = 42.1dBFS
WITHOUT NETWORK
SAMPLING RATE = 76.8MSPS
INPUT = 70MHz
NOISE FLOOR = –95dBFS
THD = –76.8dBc
SFDR = 81.4dBc
SNR = 52.8dBFS
WITH NETWORK
33. Effective Aperture Delay Time
Measured with Respect to ADC Input
33
SAMPLING
CLOCK
ANALOG INPUT
SINEWAVE
ZERO CROSSING
+FS
–FS
0V
+te
–te
te
' '
'
34. Effects of Aperture Jitter
and Sampling Clock Jitter
34
ANALOG
INPUT
TRACK
HOLD
D
dv
dt
v dv
dt
t
RMS
= APERTURE JITTER
v
RMS
NOMINAL
HELD
OUTPUT
= t
= SLOPE = APERTURE JITTER ERRORD
D
D
35. Theoretical SNR and ENOB Due to Jitter
vs. Full-Scale Sinewave Analog Input Frequency
35
SNR
(dB)
ENOB
100
80
60
40
20
16
14
12
10
8
6
4
1 3 10 30 100
tj = 1ns
tj = 100ps
tj = 10ps
tj = 1ps
tj = 0.1ps
120
18
FULL-SCALE SINEWAVE ANALOG INPUT FREQUENCY (MHz)
SNR = 20log10
1
2ftj
tj = 50fs
46. High Accuracy Sources
Resolution to 1 ppm
One microvolt out of 1 volt
Everything matters
External amplifiers – low offset, drift, noise
Voltage reference – 1 ppm drift
Layout and design
Applications
MRI – magnetic resonance imaging
Precise gradient in magnetic field
Test equipment
46
48. ADC References
Input level compared to reference
ADC accuracy is relative to that reference
Internal reference
Simplicity and lower cost
Reference tuned to ADC performance
Specifications all-inclusive
External reference
Can be chosen for higher absolute accuracy
Allows common reference in multiple-ADC system
Common reference for sensor driver and ADC
Power supply as reference
Lowest cost in most cases
Noise is biggest issue
Tolerance and drift may degrade accuracy
48
53. DAC sin x/x Roll Off
(Amplitude Normalized)
53
0.5fc fc 1.5fc 2fc 2.5fc 3fc
A =
sin
f
fc
f
fc
1
f
A
t
–3.92dB
RECONSTRUCTED
SIGNAL
0
1
fc
IMAGES
IMAGES
IMAGES
FS – FOUT FS + FOUT 2FS – FOUT 2FS + FOUT
55. Analog Filter Requirements for fo = 10 MHZ:
fc = 30 MSPS, and fc = 60 MSPS
55
fCLOCK = 30MSPS
dB
IMAGE
10 20 30 40 50 60 70 80
fo
ANALOG LPF
10 20 30 40 50 60 70 80
IMAGE
ANALOG
LPF
FREQUENCY (MHz)
IMAGE
IMAGEIMAGE
IMAGE
fo
fCLOCK = 60MSPS
dB
A
B
56. DAC Images (continued)
56
As the DAC output (FOUT) approaches Nyquist frequency, the images come closer
together, making it extremely difficult to filter the image from the signal.
0 50 100 150 200 250
0
101
102
X X X
FREQUENCY
POWER
In the above example, FOUT = 0.45 3 Fs
57. Interpolation
Maximum Output Frequency of Standard DAC is FCLOCK 2 (Nyquist Rate).
In an Interpolating D/A Converter, Digital Interpolation Filters and a PLL Clock Multiplier Are
Used to Multiply the Input Data Rate to the DAC by a Factor of x Times the Clock Rate.
Produces an Image at x Times FSIGNAL, Smoothing the Sine Function and Simplifying the
Filter Requirements and Digital Interface.
57
fSIGNAL fCLOCK = 2 x fSIGNAL fSIGNAL fCLOCK = 8 x fSIGNAL
58. AD9775 TxDAC® 14-Bit CMOS DAC Core
58
CLOCK
14-BIT
LATCH
51-BIT
LATCH
31
CURRENT
SWITCHES
15
CURRENT
5 BINARY
CURRENT
SWITCHES
BITS 1-5
DECODE
5-TO-31
BITS 6-9
DECODE
4-TO-15
5 5
15154
31 315
14
CURRENT
OUTPUT
FS =
2mA-
20mA
SWITCHES
I = 512 LSB
I = 32 LSB
I = 1 LSB
5
NOTE: Differential Outputs Not Shown
59. Oversampling Interpolating TxDAC®
Simplified Block Diagram
59
fo
K•fc
fc
LATCH LATCH DAC
LPF
DIGITAL
INTERPOLATION
FILTER
PLL
N N N N
TYPICAL APPLICATION: fc = 160MSPS
fo = 50MHz
K = 2
Image Frequency = 320– 50 = 270MHz
60. AD9772: 2X Interpolation vs.
Nyquist DAC
60
Nyquist DAC AD9772 DAC
1st IMAGE
1st NEW IMAGE
IMAGES FILTERED BY
DIGITAL 2X
INTERPOLATION
61. Tweet it out! @ADI_News #ADIDC13
What We Covered
Data converters in the signal chain
Basics of data conversion
Dynamic signal processing
Driving ADCs
Input structures
DACs for high speed and high resolution
61
62. Tweet it out! @ADI_News #ADIDC13
Design Resources Covered in This Session
Design tools & resources:
Ask technical questions and exchange ideas online in our
EngineerZone® Support Community
Choose a technology area from the homepage:
ez.analog.com
Access the Design Conference community here:
www.analog.com/DC13community
62
Name Description URL
ADIsimADC Shows dynamic performance of ADCs in real
applications
Voltage Reference
Selection Wizard
Visual Analog
SPI Controller
63. Tweet it out! @ADI_News #ADIDC13
Visit the 16-Bit 250 kSPS 8-Channel, Isolated Data
Acquisition System in the Exhibition Room
Circuits from the Lab® CN0254 is
a cost effective, highly integrated
16-bit, 250 kSPS, 8-channel data
acquisition system that can
digitize ±10 V industrial level
signals. The circuit also provides
2500 V rms isolation between the
measurement circuit and the host
controller, and the entire circuit is
powered from a single isolated
PWM controlled 5 V supply.
63
This demo board is available for purchase:
www.analog.com/DC13-hardware
64. Tweet it out! @ADI_News #ADIDC13
16-Bit 250 kSPS 8-Channel Isolated Data
Acquisition System—CN0254
64
65. The Data Conversion Handbook
65
The Data Conversion Handbook, edited by Walt Kester (Newnes,
2005), is written for design engineers who routinely use data
converters and related circuitry. Comprising Data Converter
History, Fundamentals of Sampled Data Systems, Data
Converter Architectures, Data Converter Process Technology,
Testing Data Converters, Interfacing to Data Converters, Data
Converter Support Circuits, Data Converter Applications, and
Hardware Design Techniques, it may be the ultimate expression
of product "augmentation" as it relates to data converters. The
last chapter discusses practical issues, including common pitfalls
and solutions related to the non-ideal properties of passive
components.
The Data Conversion Handbook can be purchased from your
favorite bookseller.
Individual chapters--or a zip file containing all chapters--of the original Basic Linear
Design seminar notes can be downloaded by selecting the appropriate links below
http://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_handbook.html
66. Linear Circuit Design Handbook
66
Linear Circuit Design Handbook, edited by Hank Zumbahlen
(Newnes, 2008), bridges the gap between circuit component
theory and practical circuit design. Effective analog circuit design
requires a strong understanding of core linear devices and how
they affect analog circuit design. This book provides complete
coverage of important analog devices and how to use them in
designing linear circuits, and serves as a useful learning tool and
reference for design engineers involved in analog and mixed-
signal design. It features complete coverage of analog circuit
components for the practicing engineer; market-validated design
information for all major types of linear circuits; practical advice
on how to read op amp data sheets and how to choose off-the-
shelf op amps; printed circuit board design issues; and over 1000
figures, including working circuit diagrams. Analog Dialogue
readers can get a 20% discount when they order this book
directly from Newnes. Enter discount code 92222.
Individual chapters--or a zip file containing all chapters--of the original Basic Linear
Design seminar notes can be downloaded by selecting the appropriate links below
http://www.analog.com/library/analogDialogue/archives/43-09/linear_circuit_design_handbook.html