3. A Pin of Port 1
Read latch Vcc
TB2
Load(L1)
Internal CPU D Q P1.X
bus P1.X pin
Write to latch Clk Q M1
TB1
Read pin P0.x
8051 IC

4. Writing “1” to Output Pin P1.X
Read latch Vcc
TB2
Load(L1) 2. output pin is
1. write a 1 to the pin Vcc
D Q 1 P1.X
Internal CPU
bus P1.X pin
0 output 1
Write to latch Clk Q M1
TB1
Read pin
8051 IC

5. Writing “0” to Output Pin P1.X
Read latch Vcc
TB2
Load(L1) 2. output pin is
1. write a 0 to the pin ground
D Q 0 P1.X
Internal CPU
bus P1.X pin
1 output 0
Write to latch Clk Q M1
TB1
Read pin
8051 IC

6. Reading “High” at Input Pin
Read latch Vcc 2. MOV A,P1
TB2 external pin=High
1. write a 1 to the pin MOV Load(L1)
P1,#0FFH
1 1 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q
TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC

7. Reading “Low” at Input Pin
Read latch Vcc 2. MOV A,P1
TB2
1. write a 1 to the pin Load(L1) external pin=Low
MOV P1,#0FFH
1 0 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q
TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC

8. A Pin of Port 0
Read latch
TB2
Internal CPU D Q P0.X
bus P1.X pin
Write to latch Clk Q M1
TB1
Read pin P1.x
8051 IC

9. Port 0 with Pull-Up Resistors
Vcc
10 K
P0.0
DS5000 P0.1
Port 0
P0.2
8751 P0.3
8951 P0.4
P0.5
P0.6
P0.7

12. Port 3 Alternate Functions
P3 Bit Function Pin
P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17 