Full Custom IC Design Implementation of Priority Encoder

FULL CUSTOM IC DESIGN IMPLEMENTATION OF
LOW POWER PRIORITY ENCODER
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted
By
SRIKANTH KALEMLA 10881A0452
VENKATESH VEERABATTINI 10881A0459
VISHESH THAKUR SINGH 10881A0460
BHARGAV KATKAM 11885A0401
Department of Electronic and Communication Engineering
VARDHAMAN COLLEGE OF ENGINEERING
(AUTONOMOUS)
(Approved by AICTE, Affiliated to JNTUH & Accredited by NBA)
2013 – 14

A
Project Report on
FULL CUSTOM IC DESIGN IMPLEMENTATION OF
LOW POWER PRIORITY ENCODER
Submitted in the Partial Fulfillment of the
Requirements
for the Award of the Degree of
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted
By
SRIKANTH KALEMLA 10881A0452
VENKATESH VEERABATTINI 10881A0459
VISHESH THAKUR SINGH 10881A0460
BHARGAV KATKAM 11885A0401
Under the esteemed guidance of
Mr. S. RAJENDAR
Associate Professor
Department of ECE
Department of Electronics and Communication Engineering
(AUTONOMOUS)
(Approved by AICTE, Affiliated to JNTUH & Accredited by NBA)
2013- 14

(AUTONOMOUS)
Estd.1999 Shamshabad, Hyderabad - 501218
Kacharam (V), Shamshabad (M), Ranga Reddy (Dist.) – 501 218, Hyderabad, A.P.
Ph: 08413-253335, 253201, Fax: 08413-253482, www.vardhaman.org
Department of Electronics and Communication Engineering
CERTIFICATE
This is to certify that the project work entitled “Full custom IC Design
Implementation of Low Power Priority Encoder” is done by Mr. Srikanth Kalemla
(10881A0452), Mr. Venkatesh Veerabattini (10881A0459), Mr. Vishesh Thakur
Singh (10881A0460), Mr. Bhargav Katkam (11885A0401), students of Department of
Electronics and Communication Engineering, is a record of bonafide work done by
them. This project is done as a partial fulfillment of obtaining Bachelor of
Technology degree to be awarded by Jawaharlal Nehru Technological University,
Hyderabad.
The results of investigations enclosed in this report have been verified and
found satisfactory.
External Examiner
Name & Signature of the Supervisor
Mr. S. Rajendar
Associate Professor
Name & Signature of the HOD
Dr. J. V. R. Ravindra
Head, ECE

iii
ACKNOWLEDGEMENTS
The satisfaction that accompanies the successful completion of the task would
be put incomplete without the mention of the people who made it possible, whose
constant guidance and encouragement crown all the efforts with success.
We express our heartfelt thanks to Mr. S. Rajendar, Associate Professor,
technical seminar supervisor, for his suggestions in selecting and carrying out the in-
depth study of the topic. His valuable guidance, encouragement and critical reviews
really helped to shape this report to perfection.
We wish to express our deep sense of gratitude to Dr. J. V. R. Ravindra,
Head of the Department for his able guidance and useful suggestions, which helped us
in completing the project on time.
We also owe our special thanks to our Director Prof. L. V. N. Prasad for his
intense support, encouragement and for having provided all the facilities and support.
Finally thanks to all our family members and friends for their continuous
support and enthusiastic help.
Srikanth Kalemla
Venkatesh Veerabattini
Vishesh Thakur Singh
Bhargav Katkam

iv
ABSTRACT
Today digital circuits play a prominent role in most of the communication
applications. The enhancement on a simple encoder circuit, in terms of handling all
possible input combinations has led to the development of special circuits known as
Priority Encoders. These circuits facilitate in compressing several inputs into
numerous small outputs. The quality feature of these encoders is encoding the inputs
just to make sure that only highest order lines are encoded. The result or output of the
priority encoder should be a binary representation of ordinal numbers articulated in
BCD format. In addition, these also manage interrupt requests through high priority
request. Whenever there is more than one active input at same time, then highest
priority input will be given more preference. One can find priority encoders in
standard or normal IC form such as TTL 74LS147 or TTL 74LS148. Basically, the
former encodes 9 datelines to 4 lines as in (8-4-2-1) BCD. And the latter expresses 8
datelines to 3 lines as in 4-2-1 (octal) binary. In order to provide octal expansion with
no requirement of external circuitry, one needs Cascading Circuitry. Data inputs and
data outputs are active even at low levels. Priority encoders find wide range of
applications as in keyboard encoding, range selection, bit level encoding, code
converters and generators.

v
CONTENTS
Acknowledgements iii
List of figures viii
List of tables xi
List of abbreiviations xii
1 INTRODUCTION TO PRIORITY ENCODER 1-8
1.1 What are Digital Encoders 1
1.2 Introduction to Priority Encoder 2
1.3 Primer to Digital IC Design 4
1.4 Applications of Encoders 5
1.4.1 Keyboard Encoder 5
1.4.2 Positional Encoder 6
1.4.3 Interrupt Requests 6
1.5 Organization of the report 8
2 IMPORTANCE OF VLSI 9-15
2.1 History of semiconductor 9
2.2 Development in semiconductor industry 10
2.3 Introduction to VLSI 10
2.4 The VLSI design process 11
2.4.1 A Typical Digital Design Flow is as follows 11
2.4.2 A Typical Analog Design Flow is as follows 12
2.5 Classification of VLSI design 12
2.5.1 Full Custom IC Designs 12
2.5.2 Semi-custom IC Designs 13
2.6 Some of application of VLSI 15
2.6.1 Industrial Applications 15
2.6.2 Communication Applications 15
2.6.3 Science Applications 15
3 FULL CUSTOM DESIGN FLOW 16-26
3.1 Scope and Purpose of Work 17
3.2 Design Flow 17
3.2.1 Design Specifications 19
3.2.2 Schematic Capture 19
3.2.3 Symbol Creation 20

vi
3.2.4 Simulation 20
3.2.5 Layout 21
3.2.6 Design Rule Check 22
3.2.7 LVS-Layout v/s Schematic 23
3.2.8 Circuit Extraction 24
3.2.9 Post-layout simulation 25
3.2.10 Fabrication 25
4 IMPLEMENTATION OF DESIGN 27-56
4.1 Priority encoder functioning 27
4.2 Logic gates 28
4.2.1 AND gate 28
4.2.2 OR gate 29
4.2.3 NOT gate 29
4.2.4 NAND gate 29
4.2.5 NOR gate 29
4.2.6 EXOR gate 30
4.2.7 EXNOR gate 30
4.3 Importance of layout 30
4.3.1 Automated layout 31
4.3.2 Custom layout 31
4.4 Inputs from the designer 31
4.5 From Foundry 32
4.5.1 DRC 33
4.5.2 LVS 33
4.5.3 ERC 33
4.6 Layers Classification 33
4.7 Analog Layout 34
4.7.1 Importance of Analog Layout: 34
4.8 Analog Vs Digital 34
4.9 Some of Important Analog Layout Guidelines 35
4.10 AND 2 input 39
4.11 Not Gate 40
4.12 NOR 2 input 41
4.13 NAND 2 input 42
4.14 AND 3 input 43

vii
4.15 AND 4 input 44
4.16 NOR 4 input 45
4.17 AND 5 input 46
4.18 NOR 5 input 47
4.19 NAND 9 input 48
4.20 8x3 Priority Encoder 49
4.21 10x4 Priority Encoder 52
5 CONCLUSIONS 56-58
REFERENCES 58
APPENDIX CADENCE OVERVIEW 59
Introduction 59
Schematics L 59
ADE L (Analog Design Environment) 59
Layout XL 59
Design of Schematic 60
Symbol Generation 63
SchematicSimulation 64
Calculation of Propagation Delay 65
Calculation of Power Dissipation 67
Design of Layout 67
GDS File 71

viii
LIST OF FIGURES
1.1 BCD Priority Encoder 4
1.2 Positional Encoders used as Priority Encoder Navigation 6
2.1 Full Custom IC Design 13
2.2 General architecture of Xilinx FPGAs 13
2.3 Gate Array based Design 14
2.4 Standard cell IC design 14
3.1 Typical Full Custom IC Design Flow 18
3.2 Schematic design of 4-input NOR gate. 20
3.3 Symbol view of 4-input NOR gate 20
3.4 Layout of AND gate 21
3.5 The three basic DRC checks 22
3.6 LVS Extracted netlist 23
3.7 Typical Layout versus Schematic of an Inverter 24
3.8 Parasitic Extraction 25
4.1 And gate symbol 28
4.2 OR gate symbol 29
4.3 NOT gate symbol 29
4.4 NAND gate symbol 29
4.5 NOR gate symbol 30
4.6 EXOR gate symbol 30
4.7 EXNOR gate symbol 30
4.8 2 input AND Schematic and layout 39
4.9 2 input AND symbol and test circuit 39
4.10 two input waveform 39
4.11 NOT Schematic and Layout 40
4.12 NOT Symbol and Test circuit 40
4.13 NOT Simulation waveforms 40
4.14 2 input NOR Schematic and Layout 41
4.15 2input NOR Symbol and Test circuit 41
4.16 2input NOR Simulation waveforms 41
4.17 2input NAND Schematic and Layout 42
4.18 2input NAND Symbol and Test circuit 42
4.19 2input NAND Simulation waveforms 42

ix
4.20 3input AND Schematic and Layout 43
4.21 3input AND Symbol and Test circuit 43
4.22 3input AND Simulation waveforms 43
4.26 4input NOR Schematic and Layout 45
4.27 4input NOR Symbol and Test circuit 45
4.32 5input NOR Schematic and Layout 47
4.33 5input nor Symbol and Test circuit 47
4.35 9input NAND Schematic and Layout 48
4.36 9input NAND Symbol and Test circuit 48
4.37 9input NAND Simulation waveforms 48
4.38 8x3 Priority Encoder Schematic and Layout 49
4.39 8x3 Priority Encoder Symbol and Test circuit 49
4.40 Priority Encoder Simulation waveforms without parasitics 50
4.41 8x3 Priority Encoder Simulation waveforms with parasitics 50
4.42 8x3 Priority Encoder with no DRC errors 51
4.43 8x3 Priority Encoder with no ERC errors 51
4.44 8x3 Priority Encoder with no LVS errors 51
4.45 8x3 Priority Encoder Layout with RC Extraction 52
4.46 10x4 Priority Encoder Symbol and Test circuit 52
4.47 10x4 Priority Encoder Schematic and Layout 53
4.48 10x4 Priority Encoder Simulation waveforms without parsitics 53
4.49 10x4 Priority Encoder Simulation waveforms with parasitics 54
4.50 10x4 Priority Encoder with no DRC errors 54
4.51 10x4 Priority Encoder with no ERC errors 54
4.52 10x4 Priority Encoder with no LVS errors 55
4.53 10x4 Priority Encoder Layout with RC Extraction 55
A.1 Terminal window 60

x
A.2 Virtuoso 60
A.3 New Library 61
A.4 Technology Library 61
A.5 New File 61
A.6 Instance 61
A.7 Instance Specifications 62
A.8 Schematic circuit 62
A.9 Symbol Generation 63
A.10 Symbol Specification 63
A.11 Symbol 63
A.12 ADE Window 64
A.13 Choosing Analyses 64
A.14 Save Options 65
A.15 Waveforms 65
A.16 Calculation of Propagation Delay 66
A.17 Calculation of Power Dissipation 66
A.18 New file for Layout 67
A.19 Progress on DRC 67
A.20 Assura DRC 68
A.21Errors of DRC 68
A.22 Assura LVS 69
A.23 Errors for LVS test 69
A.24 Extraction of RCX 70
A.25 RCX Generation 70
A.26 Open File for av_extracted 70
A.27 RCX 71
A.28 Stream Out 71
A.29 Stream Specification 72
A.30 Log File 72

xi
LIST OF TABLES
1.1 Function Table of Priority Encoder 2
1.2 Interrupt requests to a microprocessor 7
5.1 And gate truth table 28
5.2 And gate truth table 29
5.3 NOT gate truth table 29
5.4 NAND gate truth table 29
5.5 NOR gate truth table 30
5.6 EXOR gate truth table 30
5.7 EXNOR gate truth table 30

xii
LIST OF ABBREVIATIONS
ADE Analog Design Environment
ASG Automatic Symbol Generator
ASIC Application Specific Integrated Circuit
CAD Computer-Aided Design
CIW Command Interpreter Window
CWD Current Working Directory
DRC Design Rule Check
EDA Electronic Design Automation
EM Electron Migration
ERC Electrical Rule Check
GDS Graphic Database System
GUI Graphical User Interface
IC Integrated Circuit
LEF Library Exchange Format
LVS Layout Versus Schematic
PVT Process Voltage Temperature
RCX Resistor Capacitor Extraction
RTL Register Transfer Level
SDF Standard Delay Format
SoC System on Chip
ViVA Virtuoso Visualization and Analysis
VHSIC Very High Speed Integrated Circuit
VLSI Very Large Scale Integration

Full Custom IC Design Implementation Of Low Power Priority Encoder
Department of Electronics & Communication Engineering 1
CHAPTER 1
INTRODUCTION TO PRIORITY ENCODER
Today digital circuits play a prominent role in most of the communication
applications. In this project report an effective approach to analysis and design of
priority encoder explored and implemented using Cadence tools.
The enhancement on a simple encoder circuit, in terms of handling all possible
input combinations has led to the development of special circuits known as Priority
Encoders. These circuits facilitate in compressing several inputs into numerous small
outputs. The quality feature of these encoders is encoding the inputs just to make sure
that only highest order lines are encoded. The result or output of the priority encoder
should be a binary representation of ordinal numbers articulated in BCD format. In
addition, these also manage interrupt requests through high priority request.
Whenever there is more than one active input at same time, then highest priority input
will be given more preference. One can find priority encoders in standard or normal
IC form such as TTL 74LS147 or TTL 74LS148. Basically, the former encodes 9
datelines to 4 lines as in (8-4-2-1) BCD. And the latter expresses 8 datelines to 3 lines
as in 4-2-1 (octal) binary. In order to provide octal expansion with no requirement of
external circuitry, one needs Cascading Circuitry. Data inputs and data outputs are
active even at low levels. Priority encoders find wide range of applications as in
keyboard encoding, range selection, bit level encoding, code converters and
generators.
1.1 What are Digital Encoders
Unlike a multiplexer that selects one individual data input line and then sends
that data to a single output line or switch, a Digital Encoder more commonly called
a Binary Encoder takes all its data inputs one at a time and then converts them into a
single encoded output. So we can say that a binary encoder, is a multi-input
combinational logic circuit that converts the logic level “1″ data at its inputs into an
equivalent binary code at its output.
Generally, digital encoders produce outputs of 2-bit, 3-bit or 4-bit codes
depending upon the number of data input lines. An “n-bit” binary encoder has 2n
input
lines and n-bit output lines with common types that include 4-to-2, 8-to-3 and 16-to-4
line configurations. The output lines of a digital encoder generate the binary
equivalent of the input line whose value is equal to “1″ and are available to encode

either a decimal or hexadecimal input pattern to typically a binary or “B.C.D” (binary
coded decimal) output code.
One of the main disadvantages of standard digital encoders is that they can
generate the wrong output code when there is more than one input present at logic
level “1″. For example, if we make inputs D1 and D2 HIGH at logic “1″ both at the
same time, the resulting output is neither at “01″ or at “10″ but will be at “11″ which
is an output binary number that is different to the actual input present. Also, an output
code of all logic “0″s can be generated when all of its inputs are at “0″ OR when input
D0 is equal to one.
One simple way to overcome this problem is to “Prioritise” the level of each
input pin and if there was more than one input at logic level “1″ the actual output code
would only correspond to the input with the highest designated priority. Then this
type of digital encoder is known commonly as a Priority Encoder or P-encoder for
short.
1.2 Introduction to Priority Encoder
A priority encoder is a circuit or algorithm that compresses multiple binary
inputs into a smaller number of outputs. The output of a priority encoder is the binary
representation of the original number starting from zero of the most significant input
bit. They are often used to control interrupt requests by acting on the highest priority
request.
Priority encoders can be easily connected in arrays to make larger encoders,
such as one 16-to-4 encoder made from six 4-to-2 priority encoders - four 4-to-2
encoders having the signal source connected to their inputs, and the two remaining
encoders take the output of the first four as input. The priority encoder is an
improvement on a simple encoder circuit, in terms of handling all possible
input configurations. The simplified function table of the four input level priority
encoder circuit is indicated in table below.
Table 1.1 Function Table of Priority Encoder
If two or more inputs are given at the same time, the input having the highest

priority will take precedence. An example of a single bit 4 to 2 encoder is shown,
where highest-priority inputs are to the left and "x" indicates an irrelevant value - i.e.
any input value there yields the same output since it is superseded by higher-priority
input. The output V indicates if the input is valid.
The Priority Encoder solves the problems mentioned above by allocating a
priority level to each input. The priority encoders output corresponds to the currently
active input which has the highest priority. So when an input with a higher priority is
present, all other inputs with a lower priority will be ignored. The priority encoder
comes in many different forms with an example of an 8-input priority encoder along
with its truth table shown below.
Priority encoders are available in standard IC form and the TTL 74LS148 is an
8-to-3 bit priority encoder which has eight active LOW (logic “0″) inputs and
provides a 3-bit code of the highest ranked input at its output. Priority encoders output
the highest order input first for example, if input lines “D2“, “D3” and “D5” are
applied simultaneously the output code would be for input “D5” (“101″) as this has
the highest order out of the 3 inputs. Once input “D5” had been removed the next
highest output code would be for input “D3” (“011″), and so on.
As indicated in Table 1.1along with two functional output levels one more
output level namely valid bit indicator indicates the correct input levels. If all the
input levels are equal to zero then the valid bit indicator indicates its output as low
output and otherwise it indicates the output level at high state. Because of the
simplified form the function table it is not indicated for all the possible input
combinations and only indicates the few input combinations and X in the table
indicates whether the input level is either active high or active low. Based on the table
the greater priority will be given on input level D3 then followed by other input levels
D2, D1 and D0 respectively. When the input level D3 is active high then there is no need
for verify the other input levels likewise if D3 is in active low then D2 is active high
then C will be higher priority level compared to other input levels. The karnaugh map
is providing a simple procedure for simplifying the given Boolean function. This
method provides a pictorial form of a function table. A karnaugh map is a diagram
and it is made up of squares with each square represent a min term of the function that
is to be simplified.
Figure 1.1 shows an example of the operation of a BCD priority encoder.
In Figure 1.1a, only input D2 is active, so the output code generated is 0010,
the binary equivalent of 2. In Figure 1.1b, input D2 remains active, but now D7 is also

active. Since D7 has the higher priority, the output code is now 0111, the binary
equivalent of 7. InFigure 1.1c, input D9 is HIGH, in addition to the other two inputs.
Since D9 has the highest priority, the output is 1001. There is no input for D0 since
the output 0000 is the default value when no inputs are active.
D1
D2
D3
D4
D5
D6
D7
D8
D9
Q0
Q1
Q2
Q3
D1
D2
D3
D4
D5
D6
D7
D8
D9
Q0
Q1
Q2
Q3
D1
D2
D3
D4
D5
D6
D7
D8
D9
Q0
Q1
Q2
Q3
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
1
1
1
1
0
0
1
A.priority:2 B.priority:7 C.priority:9
Figure 1.1 BCD Priority Encoder
1.3 Primer to Digital IC Design
IC design can be divided into the broad categories of digital and analog IC
design. Digital IC design is to produce components such as microprocessors, FPGAs,
memories (RAM, ROM, and flash) and digital ASICs. Digital design focuses on
logical correctness, maximizing circuit density, and placing circuits so that clock and
timing signals are routed efficiently. Analog IC design also has specializations in
power IC design and RF IC design. Analog IC design is used in the design of op-
amps, linear regulators, phase locked loops, oscillators and active filters. Analog
design is more concerned with the physics of the semiconductor devices such as gain,
matching, power dissipation, and resistance. Fidelity of analog signal amplification
and filtering is usually critical and as a result, analog ICs use larger area active
devices than digital designs and are usually less dense in circuitry.
Full-custom design is a methodology for designing integrated circuits by
specifying the layout of each individual transistor and the interconnections between
them.
Alternatives to full-custom design include various forms of semi-custom
design, such as the repetition of small transistor sub circuits; one such methodology is
the use of standard cell libraries (standard cell libraries are themselves designed using

full-custom design techniques). In addition it will make extensive use of CAD tools
for IC design, simulation. Specific techniques for designing high-speed, low-power,
and easily-testable circuits will also be covered. Full-custom design potentially
maximizes the performance of the chip, and minimizes its area, but is extremely
labour-intensive to implement. Full-custom design is limited to ICs hat are to be
fabricated in extremely high volumes, notably certain microprocessors and a small
number of ASICs.
Semiconductor technology continues to attract enormous investment and is
available to anyone with the know-how to use it. It is used not only to design complex
high density circuits but also chemical and medical sensors, ASICS (application
specific integrated circuits) of many types.
IC design requires an understanding of the fabrication process, digital
electronics and makes use of a range of important CAD tools as listed below. The
objective of this course is to illustrate the complete design cycle and produce a fully
verified simple design ready for fabrication. This will provide literacy in one of the
dominant technologies of the time. This introduction will not make you into a
designer but will give you a literacy in the area of integrated circuit design which is
lacking in most physicists.
The expertise in IC design is concentrated in volume silicon devices and low
volume, specialist ASICs are relatively neglected. This is partly for financial reasons
and partly because the idea for a new ASIC is in the head of the inventor only.
The skills needed include an understanding of the basics of:
a) electronics including digital electronics
b) software design tools
c) Silicon fabrication technology. This may not be necessary if there are
no non-standard fabrication steps.
Beyond this the main requirement is an ability to solve problems which will
inevitably arise. New programmable chips are now available which enable immediate
implementation of a circuit designed on computer. These devices may be
reprogrammed and offer a very attractive option where hand crafted design is not
necessary and only small number units are needed.
1.4 Applications of Encoders
Digital Encoders find wide range of applications as shown below:
1.4.1 Keyboard Encoder

Priority encoders can be used to reduce the number of wires needed in a
particular circuits or application that has multiple inputs. For example, assume that a
microcomputer needs to read the 104 keys of a standard QWERTY keyboard where
only one key would be pressed either “HIGH” or “LOW” at any one time.
One way would be to connect all 104 wires from the individual keys on the
keyboard directly to the computers input but this would be impractical for a small
home PC. Another alternative and better way would be to interface the keyboard to
the PC using a priority encoder.
The 104 individual buttons or keys could be encoded into a standard ASCII
code of only 7-bits (0 to 127 decimal) to represent each key or character of the
keyboard and then inputted as a much smaller 7-bit B.C.D code directly to the
computer. Keypad encoders such as the 74C923 20-key encoder are available to do
just that.
1.4.2 Positional Encoder
Another more common application is in magnetic positional control as used on
ships navigation or for robotic arm positioning etc. Here for example, the angular or
rotary position of a compass is converted into a digital code by a 74LS148 8-to-3 line
priority encoder and inputted to the systems computer to provide navigational data
and an example of a simple 8 position to 3-bit output compass encoder is shown
below. Magnets and reed switches could be used at each compass point to indicate the
needles angular position.
Figure 1.2 Positional Encoders used as Priority Encoder Navigation
1.4.3 Interrupt Requests
Other applications especially for Priority Encoders may include detecting
interrupts in microprocessor applications. As illustrated in table 1.2 below here the
microprocessor uses interrupts to allow peripheral devices such as the disk drive,
scanner, mouse, or printer etc., to communicate with it, but the microprocessor can

only “talk” to one peripheral device at a time so needs some way of knowing when a
particular peripheral device wants to communicate with it.
The processor does this by using “Interrupt Requests” or “IRQ” signals to
assign priority to all the peripheral devices to ensure that the most important
peripheral device is serviced first. The order of importance of the devices will depend
upon their connection to the priority encoder.
Table 1.2 Interrupt requests to a microprocessor
Because implementing such a system using priority encoders such as the
standard 74LS148 priority encoder IC involves additional logic circuits, purpose built
integrated circuits such as the 8259 Programmable Priority Interrupt Controller is
available.
Then to summarise, the Digital Encoder is a combinational circuit that
generates a specific code at its outputs such as binary or BCD in response to one or
more active inputs. There are two main types of digital encoder:-The Binary
Encoder and the Priority Encoder.
We have seen that the Binary Encoder converts one of 2n
inputs into an n-
bit output. Then a binary encoder has fewer output bits than the input code. Binary
encoders are useful for compressing data and can be constructed from
simple AND or OR gates. One of the main disadvantages of a standard binary encoder
is that it would produce an error at its outputs if more than one input were active at the
same time. To overcome these problem priority encoders were developed.
The Priority Encoder is another type of combinational circuit similar to a

binary encoder, except that it generates an output code based on the highest prioritised
input. Priority encoders are used extensively in digital and computer systems as
microprocessor interrupt controllers where they detect the highest priority input.
1.5 Organization of the report
This report starts with an overview of the priority encoder giving importance
to the full custom design. The report also include the implementation of the design
done by using Cadence tools that accurately generated that results and its easily
modifiable graphical representation of the product proved advantageous. We analyse
the impact of area, power consumption and delay, and introduce techniques to cope
with power consumption. These variations fundamentally limit the performance that
can be achieved using a conventional design methodology. The report is organized as
follows:
Chapter 1: Introduction To Priority Encoder - This chapter briefly explains the
overview of the report.
Chapter 2: Importance of VLSI - This chapter describes the growing evolution of
VLSI in today’s world and also lists some of its applications in various fields.
Chapter 3: Full Custom Design Flow - This chapter presents the detailed design flow
of full custom IC design.
Chapter 4: Implementation of Design – This chapter designates the implementation of
priority encoder (74LS147 & 74LS148) carried out using Cadence EDA tools.
Chapter 5: Conclusions - This chapter summarizes the major accomplishments of this
report.

CHAPTER 2
IMPORTANCE OF VLSI
2.1 History of semiconductor
Before 1960, most electronic circuits depended upon vacuum tubes to perform
the critical tasks of amplification and rectification. An ordinary mass-produced AM
radio required five tubes, while a colour television needed no fewer than twenty.
Vacuum tubes were large, fragile and expensive. They dissipated a lot of heat and
were not very reliable. So long as Electronics depended upon them, it was nearly
impossible to construct systems requiring thousands or millions of active devices.
The appearance of the bipolar junction transistor in 1947 marked the
beginning of the solid state revolution. These new devices were cheap, small, rugged
and reliable. Solid state circuitry made possible the development compact disc
players, pocket transistor radios and personal computers.
“A solid state device consists of a crystal with regions of impurities
incorporated in to its surface. These impurities modify the electrical properties of the
crystal, allowing it to amplify or modulate electrical signals.”
So as the technology is growing up newer type of transistors came into
existence .BJT was popular for many years but due to its disadvantages such as power
dissipation, speed of operation it has becoming less popular. Metal Oxide Silicon
Transistor (MOST) which was invented earlier than BJT'S but was not produced due
to lack of production techniques at that time. Researches are carried on to reduce
larger power consumption, size and speed of MOST, evolving simple techniques
for MOS Integrated circuits production.
The first practical Integrated circuit appeared in 1960. These consisted of a
few dozen bipolar transistors and diffused resistors connected to form simple logic
gates. By modern standards, these early integrated circuits were terribly slow and
inefficient. Refinements were soon made, and the first analog integrated circuits
appeared, these consisted of matched transistor arrays, operational amplifiers and
voltage references.
Integrated bipolar logic was fast but power-hungry. MOS integrated circuits
held out the promise of a lower-power alternative, but the metal-gate MOS processes
of the 1960s suffered from unpredictable threshold voltage shifts. This problem was
eventually conquered through the development of polysilicon-gate MOS processes.

Now in the present technology the transistor that is leading the technology is
the CMOS simply called as Complementary Metal oxide Semiconductor.
2.2 Development in semiconductor industry
The first semiconductor chips held two transistors each. Subsequent advances
added more and more transistors, and, as a consequence, more individual functions or
systems were integrated over time. The first integrated circuits held only a few
devices, perhaps as many as ten Diodes, Transistors, Resistors and Capacitors making
it possible to fabricate one or more logic gates on a single device. Now known
retrospectively as Small Scale Integration (SSI), improvements in technique led to
devices with hundreds of logic gates, known as Medium Scale Integration (MSI).
Further improvements led to Large Scale Integration (LSI), i.e. systems with at least a
thousand logic gates. Current technology has moved far past this mark and today's
microprocessors have many millions of gates and billions of individual transistors.
2.3 Introduction to VLSI
VLSI stands for "Very Large Scale Integration". This is the field which
involves packing more and more logic devices into smaller and smaller areas. Thanks
to VLSI, circuits that would have taken board full of space can now be put into a
small space few millimetres across! This has opened up a big opportunity to do things
that were not possible before. VLSI circuits are everywhere ... your computer, your
car, your brand new state-of-the-art digital camera, the cell-phones, and what have
you. All this involves a lot of expertise on many fronts within the same field, which
we will look at in later sections.
VLSI has been around for a long time, there is nothing new about it but as a
side effect of advances in the world of computers, there has been a dramatic
proliferation of tools that can be used to design VLSI circuits. Alongside, obeying
Moore's law, the capability of an IC has increased exponentially over the years, in
terms of computation power, utilisation of available area, yield. The combined effect
of these two advances is that people can now put diverse functionality into the IC's,
opening up new frontiers. Examples are embedded systems, where intelligent devices
are put inside everyday objects, and ubiquitous computing where small computing
devices proliferate to such an extent that even the shoes you wear may actually do
something useful like monitoring your heartbeats! These two fields are kind a related
and getting into their description can easily lead to another article.
Digital VLSI circuits are predominantly CMOS based. The way normal blocks

like latches and gates are implemented is different from what students have seen so
far, but the behaviour remains the same. All the miniaturisation involves new things
to consider. A lot of thought has to go into actual implementations as well as design.
Let us look at some of the factors involved.
1. Circuit Delays. Large complicated circuits running at very high frequencies have
one big problem to tackle - the problem of delays in propagation of signals through
gates and wires ... even for areas a few micrometres across! The operation speed is so
large that as the delays add up, they can actually become comparable to the clock
speeds.
2. Power. Another effect of high operation frequencies is increased consumption of
power. This has two-fold effect - devices consume batteries faster, and heat
dissipation increases. Coupled with the fact that surface areas have decreased, heat
poses a major threat to the stability of the circuit itself.
3. Layout. Laying out the circuit components is task common to all branches of
electronics. What’s so special in our case is that there are many possible ways to do
this; there can be multiple layers of different materials on the same silicon, there can
be different arrangements of the smaller parts for the same component and so on.
The power dissipation and speed in a circuit present a trade-off; if we try to optimise
on one, the other is affected. The choice between the two is determined by the way we
chose the layout the circuit components. Layout can also affect the fabrication of
VLSI chips, making it either easy or difficult to implement the components on the
silicon.
2.4 The VLSI design process
2.4.1 A Typical Digital Design Flow is as follows
Specification Architecture RTL Coding RTL Verification Synthesis Backend
Tape Out to Foundry to get end product. A wafer with repeated number of identical
IC’s.
All modern digital designs start with a designer writing a hardware
description of the IC (using HDL or Hardware Description Language) in
Verilog/VHDL. A Verilog or VHDL program essentially describes the hardware
(logic gates, Flip-Flops, counters etc.) and interconnect of circuit blocks and the
functionality. Various CAD tools are available to synthesize a circuit based on the
HDL. The most widely used synthesis tools come from two CAD companies.
Synposys and Cadence.

Without going into details, we can say that the VHDL can be called as the "C"
of the VLSI industry. VHDL stands for "VHSIC Hardware Definition Language",
where VHSIC stands for "Very High Speed Integrated Circuit". This language is used
to design the circuits at a high-level, in two ways. It can either be a behavioural
description, which describes what the circuit is supposed to do, or a structural
description, which describes what the circuit is made of. There are other languages for
describing circuits, such as Verilog, which work in a similar fashion. Both forms of
description are then used to generate a very low-level description that actually spells
out how all this is to be fabricated on the silicon chips. This will result in the
manufacture of the intended IC.
2.4.2 A Typical Analog Design Flow is as follows
In case of analog design, the flow changes somewhat. Specifications
Architecture Circuit Design SPICE Simulation Layout Parametric Extraction / Back
Annotation Final Design Tape Out to foundry.
While digital design is highly automated now, very small portion of analog
design can be automated. There is a hardware description language called AHDL but
is not widely used as it does not accurately give us the behavioral model of the circuit
because of the complexity of the effects of parasitic on the analog behavior of the
circuit. Many analog chips are what are termed as “flat” or non-hierarchical designs.
This is true for small transistor count chips such as an operational amplifier, or a filter
or a power management chip. For more complex analog chips such as data converters,
the design is done at a transistor level, building up to a cell level, then a block level
and then integrated at a chip level. Not many CAD tools are available for analog
design even today and thus analog design remains a difficult art. SPICE remains the
most useful simulation tool for analog as well as digital design.
2.5 Classification of VLSI design
VLSI designs can be classified into the following based on the effort
required for designing.
2.5.1 Full Custom IC Designs
These designs include logic cells which are customized and all mask layers
are also customized specific to the design. This approach is generally taken when
there are no suitable existing cell libraries available that can be used for the entire
design. This type of designs involves a lot of manual work and attention towards the
specs of the design.

Figure 2.1 Full Custom IC Design
2.5.2 Semi-custom IC Designs
These designs include logic cells which are predesigned and some of mask
layers are customized specific to a design. Cell libraries contain all the predesigned &
characterized cells. Semi-custom IC designs are further classified in to two categories:
a)Field Programmable Gate Array
Fully fabricated FPGA chips containing thousands of logic gates or even
more, with programmable interconnects, are available to users for their custom
hardware programming to realize desired functionality. This design style provides a
means for fast prototyping and also for cost-effective chip design, especially for low-
volume applications. A typical field programmable gate array (FPGA) chip consists of
I/O buffers, an array of configurable logic blocks (CLBs), and programmable
interconnect structures. The programming of interconnects is implemented by
programming of RAM cells whose output terminals are connected to the gates of
MOS pass transistors. A general architecture of FPGA from XILINX is shown
Figure 2.2 General architecture of Xilinx FPGAs

b) Gate array based IC designs
In gate array based IC designs the transistors are predefined on the silicon
wafer. The predefined pattern of transistor on a gate array is the base array and
smallest element that is replicated to make the base array is the base cell. Only the top
few layers of metal, which define the interconnect between transistors are defined by
the designer using custom masks.
This type of IC designs contains the logic cells which are in gate array library.
The logic cells in the gate array library are often called Macro's.
Figure 2.3 Gate Array based Design
c) Standard Cell Based IC designs
It uses predesigned logic cells (AND, OR, MUX and Flip-Flop's) known as
standard cells. These standard cells may be used in combination with larger
predesigned cells such as Micro controllers, Microprocessors, etc. The advantage of
Standard Cell Based IC designs is that designers save time, money and reduce risk by
using a predesigned, pretested and precharacterized standard cell library.
Figure 2.4 Standard cell IC design

2.6 Some of application of VLSI
2.6.1 Industrial Applications
• Microcontrollers & Microprocessors.
• Interfacing circuits.
• Image sensors.
• Robotics.
2.6.2 Communication Applications
• Modulators.
• Demodulators.
• Cellular handset
• Modems.
• Data converters.
• Frequency synthesizers.
2.6.3 Science Applications
• Automated devices.
• Developing sophisticated tools
• In astronomy.
In oceanography.

CHAPTER 3
FULL CUSTOM DESIGN FLOW
While digital design is highly automated now, very small portion of analog
design can be automated. There is a hardware description language called AHDL but
is not widely used as it does not accurately give us the behavioral model of the circuit
because of the complexity of the effects of parasitic on the analog behavior of the
circuit. Many analog chips are what are termed as “flat” or non-hierarchical designs.
This is true for small transistor count chips such as an operational amplifier, or a filter
or a power management chip. For more complex analog chips such as data converters,
the design is done at a transistor level, building up to a cell level, then a block level
and then integrated at a chip level. Not many CAD tools are available for analog
design even today and thus analog design remains a difficult art. SPICE remains the
most useful simulation tool for analog as well as digital design.
These designs include logic cells which are customized and all mask layers are
also customized specific to the design. This approach is generally taken when there
are no suitable existing cell libraries available that can be used for the entire design.
This type of designs involve a lot of manual work and attention towards the specs of
the design.
The back-end design of layout implementation known as integrated circuit
(IC) layout -- is simplistically divided into ASIC-style flow and full-custom flow.
This article will try to help users define the various flavors of full-custom layout. The
concepts presented here apply in general. However, the examples and references
shown refer primarily to CMOS layout design. For a newcomer to VLSI design, full-
custom flow means polygon-level layout done entirely through the use of simple
polygon pusher software. A lot of people around the world perform this function and
common wisdom says the only solution to increasing the quantity and speed of layout
is to hire more people. In reality, there are four distinct flavors of full-custom layout
design and each offers a range of possibilities for automation:
• Full-custom layout driven by area limitations or special application needs: This
type of layout is made up of repeated complex structures like sense amplifiers,
decoders, adders, multipliers -- in general, a datapath with tight control over area,
signal noise, bit symmetry. We refer to this type of layout as "datapath layout."

• Full-custom layout to address high performance or analog circuitry design: This
includes phase-locked loops (PLLs), digital-to-analog converters or analog-to-
digital converters (DACs/ADCs), electrostatic discharge (ESD) structures,
regulators, radio frequency (RF) speed requirements, or techniques to meet low-
power needs. Let's call this type of layout "analog layout."
• Full-custom layout that requires greater attention to area and performance than the
full digital (ASIC) flow, but has less stringent requirements for speed and less
need for control over device-level layout than datapath or analog layout: We call
this type of layout "custom digital layout."
• Full-custom layout for cell development: Cells are defined as logical building
blocks that are part of a family of components that share common abutment rules,
performance characteristics, or functionality. Examples would include the cells
within a standard cell library or family of Pad cells. Let's call this type of layout
"cell layout."
3.1 Scope and Purpose of Work
Full custom layout usually enables the layout designer to pack his devices in a
smaller area compared to the automated process but it is more tedious. The automated
process, on the other hand, is done using standard cells and usually takes more real
estate space but it is much faster. Layout is done by using different tools such as
Layout plus editor, Layout XL tool etc.
Verification checks are essential to any successful layout design, since they
account for the various allowances that need to be given during actual fabrication and
to account for the sizes and the steps involved in generating masks for the final layout.
The layout is very much process dependent, since every process has a certain fixed
number of available masks for layout and fabrication. In the design flow, after layout
the verification process is also very important. There are many failure mechanisms in
IC design and fixing the error is very expensive. We should take the approach that we
only have one chance to get our design right, because a revision to a design is a very
lengthy and costly process. A robust verification plan is required for best results.
3.2 Design Flow
The full custom Integrated circuit design flow is illustrated below. To facilitate
coordination, design and layout are developed in a full concurrent engineering style.
The designer tries a new solution and the layout must match it in the pitch-limited
spot. For such a design style, a flow that allows architecture exploration and fast back

annotation to design is a must.
Figure 3.1 Typical Full Custom IC Design Flow
As seen in the above figure the flow starts with the design specification from
the customer which includes all the system requirements. Then comes the schematic
capture in which various components pertaining to the required design are placed and
are interconnected and there after the design and checked and saved to verify proper
functioning.
The flow from layout to design and back can iterate as often as five or ten
times. And yet, a "good solution" may still not be "clean" when passing through
verification. Due to the nature of the processes in this case, we may be forced back to
schematic design for small adjustments. Simulation involves capturing the design
schematic and further creating its symbol then the setup is requires to be analysed
with Analog Design Environment along with the input for simulation. A layout is
basically a drawing of the masks from which the design will be fabricated.
“Therefore, layout is just as critical as specifying the parameters of your devices
because it determines whether yours is a working design or a flop.” After the layout is

been done comes the physical verification checks that include three essential checks-
DRC, LVS and ERC. In order to reduce the complexity of the circuit in terms of
power consumed the parasitic extraction is performed and the relevant simulation and
re-evaluation with and without parasitics is accomplished. Finally if it agrees all the
design specified rules it’s then sent for fabrication. The typical full custom IC design
flow is explained in detail below.
3.2.1 Design Specifications
The design flow for a transistor-level circuit layout always starts with a set of
design specifications.
The "specs" typically describe the expected functionality (Boolean operations)
of the designed block, Such as the maximum allowable delay times, the silicon area
and other properties such as power dissipation. Usually, the design specifications
allow considerable freedom to the circuit designer on issues concerning the choice of
a specific circuit topology, individual placement of the devices, the locations of input
and output pins, and the overall aspect ratio (width-to-height ratio) of the final design.
Note that the limitations spelled out in the initial design specs typically require certain
design tradeoff, such as increasing the dimensions of the transistors in order to reduce
the delay times.
3.2.2 Schematic Capture
Schematic is created at transistor level or gate level using a schematic editor.
These editors provide simple, intuitive means to draw, to place and to connect
individual components that make a design reaching required specs. The resulting
schematic drawing must accurately describe the main electrical properties of all
components and their interconnections.
Schematic also includes power and ground connections, as well as all pins for
input and output signals of a circuit. The generation of a complete circuit is therefore
the first important step of the transistor level design flow.
The view of schematic diagram is shown in the figure 2.2 below.
Some properties of the components and the interconnections between the
devices are subsequently modified as a result of iterative optimization steps. These
later modifications and improvements on the circuit must also accurately reflected in
the most current version of the corresponding schematic. The design of schematic is
by keeping the layout considerations in mind like, whether device values realizable in
layout, giving same W/L ratio for matching transistors, preferring the sizes of devices
keeping area in consideration, etc.

Figure 3.2 Schematic design of 4-input NOR gate.
3.2.3 Symbol Creation
A circuit design may consist of smaller hierarchical components, to identify
such modules in design process a symbol will be created which corresponds to that
particular module. This process largely simplifies the schematic representation of the
complete system. The symbol view of a circuit module stands for collection of all
components within the module. A symbol view of the circuit is also required for some
of the subsequent simulation steps, thus the schematic capture of the circuit topology
is usually followed by the creation of a symbol to represent the entire circuit. This
icon as shown in figure 2.3 can now be used as the building block of another module.
Figure 3.3 Symbol view of 4-input NOR gate
3.2.4 Simulation
After transistor level description of circuit using schematic editor, the
electrical performance and the functionality of the circuit must be verified using a
simulation tool. Based on simulation results, the designer usually modifies some of
the device properties in order to optimize the performance. The detailed transistor

level simulation of design will be the first in depth validation of its operation, hence it
is extremely important to complete this step before proceeding with the subsequent
design optimization steps.
3.2.5 Layout
Layout is nothing but the preparation of masks of a particular design. The
layout designer describes the detailed geometry's and the relative positioning of each
mask layer to be used in actual fabrication, using a layout editor. Physical layout
design is very tightly linked to overall circuit performance like area usage, speed,
power dissipated, etc. as the physical structure determines the transconductance of the
transistors. The detailed mask layout of logic gates requires very intensive and time
consuming design efforts.
Figure 3.4 Layout of AND gate
The physical design of CMOS logic gates is an iterative process, which starts
with the circuit topology and initial sizing of the transistors. It is extremely important
that the layout must not violate any of design rule, in order to ensure a high
probability of defect free fabrication of all features described in the mask layout.
Another alternative of generating the mask layout is to make use of automated tools.
This will generate a layout from a schematic using the device level placer. Analog
layout is the place where the layout designer needs to understand the phenomena that
happens within the devices, physical connections, implants, and needs to have a good
knowledge of semiconductor physics. For example, in a design operating at speeds up

to 10 GHz, each small detail that is forgotten will impact performance. This is the
place where a layout designer can enhance or destroy a design performance based on
his or her capability to apply proper methodologies for each type of circuit. Interlaced
devices, common centroid placement and connectivity, differential pairs routing,
substrate noise and jitter -- all of them are playing a crucial role in the cell/block
performance. Unlike other types of design, analog design deals with capacitors,
resistors, and inductors; automation is often seen as impossible.
3.2.6 Design Rule Check
The created mask layout must conform to a complex set of design rules, in
order to ensure a lower probability of fabrication defects. A tool built into the Layout
Editor, called Design Rule Checker, is used to detect any design rule violations during
and after the mask layout design.
The detected errors are displayed on the layout editor window as error
markers, and the corresponding rule is displayed in a separate window. The designer
must perform DRC (in a large design, DRC is usually performed frequently - before
the entire design is completed), and make sure that all layout errors are eventually
removed from the mask layout, before the final design is saved.
The most basic design rules are shown in the diagram below. The first are
single layer rules. A width rule specifies the minimum width of any shape in the
design. A spacing rule specifies the minimum distance between two adjacent objects.
These rules will exist for each layer of semiconductor manufacturing process, with the
lowest layers having the smallest rules and the highest metal layers having larger
rules.
Figure 3.5 The three basic DRC checks
A two layer rule specifies a relationship that must exist between two layers.
For example, an enclosure rule might specify that an object of one type, such as a
contact or via, must be covered, with some additional margin, by a metal layer.
There are many other rule types not illustrated here. A minimum area rule is
just what the name implies. Antenna rules are complex rules that check ratios of areas

of every layer of a net for configurations that can result in problems when
intermediate layers are etched. Many other such rules exist and are explained in detail
in the documentation provided by the semiconductor manufacturer.
Academic design rules are often specified in terms of a scalable parameter, λ,
so that all geometric tolerances in a design may be defined as integer multiples of λ.
This simplifies the migration of existing chip layouts to newer processes. Industrial
rules are more highly optimized, and only approximate uniform scaling. Design rule
sets have become increasingly more complex with each subsequent generation of
semiconductor process.
3.2.7 LVS-Layout v/s Schematic
Circuit extraction is performed after the mask layout design is completed, in
order to create a detailed netlist (or circuit description) for the simulation tool. The
circuit extractor is capable of identifying the individual transistors and their
interconnections (on various layers), as well as the parasitic resistances and
capacitance s that are inevitably present between these layers. Shown below is an
example of the extracted report after LVS check is been performed.
Figure 3.6 LVS Extracted netlist
Thus, the "extracted net-list" can provide a very accurate estimation of the
actual device dimensions and device parasitic that ultimately determines the circuit
performance. The extracted net-list file and parameters are subsequently used in
Layout-versus-Schematic comparison and in detailed transistor-level simulations
(post-layout simulation).

In most cases the layout will not pass LVS the first time requiring the layout
engineer to examine the LVS software's reports and make changes to the layout.
Typical errors encountered during LVS include:
1. Shorts: Two or more wires that should not be connected have been and must be
separated.
2. Opens: Wires or components that should be connected are left dangling or only
partially connected. These must be connected properly to fix this.
3. Component Mismatches: Components of an incorrect type have been used (e.g. a
low Vt MOS device instead of a standard Vt MOS device)
4. Missing Components: An expected component has been left out of the layout.
5. Parameter Mismatch: Components in the netlist can contain properties. The LVS
tool can be configured to compare these properties to a desired tolerance. If this
tolerance is not met, then the LVS run is deemed to have a Property Error. A
parameter that is checked may not be an exact match, but may still pass if the LVS
tool tolerance allows it. (example: if a resistor in a schematic had resistance=1000
(ohms) and the extracted netlist had the a matched resistor with
resistance=997(ohms) and the tolerance was set to 2%, then this device parameter
would pass as 997 is within 2% of 1000 ( 997 is 99.7% of 1000 which is within
the 98% to 102% range of the acceptable +-2% tolerance error) )
Figure illustrating LVS check of an inverter is shown below.
Figure 3.7 Typical Layout versus Schematic of an Inverter
3.2.8 Circuit Extraction
Circuit extraction is performed after the mask layout design is completed, in
order to create a detailed netlist (or circuit description) for the simulation tool. The
circuit extractor is capable of identifying the individual transistors and their

interconnections (on various layers), as well as the parasitic resistances and
capacitance s that are inevitably present between these layers. Thus, the "extracted
net-list" can provide a very accurate estimation of the actual device dimensions and
device parasitic that ultimately determines the circuit performance. The extracted net-
list file and parameters are subsequently used in Layout-versus-Schematic comparison
and in detailed transistor-level simulations (post-layout simulation).
Figure 3.8 Parasitic Extraction
3.2.9 Post-layout simulation
The electrical performance of a full-custom design can be best analyzed by
performing a post-layout simulation on the extracted circuit net-list. At this point, the
designer should have a complete mask layout of the intended circuit/system, and
should have passed the DRC and LVS steps with no violations. The detailed
(transistor level) simulation performed using the extracted net-list will provide a clear
assessment of the circuit speed, the influence of circuit parasitic (such as parasitic
capacitance s and resistances), and any glitches that may occur due to signal delay
mismatches.
If the results of post-layout simulation are not satisfactory, the designer should
modify some of the transistor dimensions and/or the circuit topology, in order to
achieve the desired circuit performance under "realistic" conditions, i.e., taking into
account all of the circuit parasitic. This may require multiple iterations on the design,
until the post-layout simulation results satisfy the original design requirements.
Finally, note that a satisfactory result in post-layout simulation is still no
guarantee for a completely successful product; the actual performance of the chip can
only be verified by testing the fabricated prototype. Even though the parasitic
extraction step is used to identify the realistic circuit conditions to a large degree from
the actual mask layout, most of the extraction routines and the simulation models used
in modern design tools have inevitable numerical limitations. This should always be
one of the main design considerations, from the very beginning.
3.2.10 Fabrication

Finally ICs are fabricated in a layer process which includes three key process
steps – imaging, deposition and etching. The main process steps are supplemented by
doping and cleaning.
Integrated circuits are composed of many overlapping layers, each defined by
photolithography, and normally shown in different colors. Some layers mark where
various dopants are diffused into the substrate (called diffusion layers), some define
where additional ions are implanted (implant layers), some define the conductors
(polysilicon or metal layers), and some define the connections between the conducting
layers (via or contact layers). All components are constructed from a specific
combination of these layers.
The CMOS fabrication technology requires both n-channel (nMOS) and p-
channel (pMOS) transistors built on the same chip substrate. To accommodate both
nMOS and pMOS devices, special regions must be created in which the
semiconductor type is opposite to the substrate type. These regions are called wells or
tubs. A p-well is created in an n-type substrate or, alternatively, an n- well is created
in a p-type substrate. In the simple n-well CMOS fabrication technology presented,
the nMOS transistor is created in the p-type substrate, and the pMOS transistor is
created in the n-well, which is built-in into the p-type substrate. In the twin-tub
CMOS technology, additional tubs of the same type as the substrate can also be
created for device optimization.

CHAPTER 4
IMPLEMENTATION OF DESIGN
4.1 Priority encoder functioning
In designing 10-line to 4-line and 8-line to 3-line priority encoders several
modules that is he basic gates are required where each and every gate has its proper
working operation. The SN54/74LS147 and the SN54/74LS148 are Priority Encoders.
They provide priority decoding of the inputs to ensure that only the highest order data
line is encoded. Both devices have data inputs and outputs which are active at the low
logic level. The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The
implied decimal zero condition does not require an input condition because zero is
encoded when all nine data lines are at a high logic level. The LS148 encodes eight
data lines to three-line (4-2-1) binary (octal). By providing cascading circuitry
(Enable Input EI and Enable Output EO) octal expansion is allowed without needing
external circuitry. The SN54/74LS748 is a proprietary Motorola part incorporating a
built-in deglitcher network which minimizes glitches on the GS output. The glitch
occurs on the negative going transition of the EI input when data inputs 0–7 are at
logical ones. The only dc parameter differences between the LS148 and the LS748 are
that (1) Pin 10 (input 0) has a fan-in of 2 on the LS748 versus a fan-in of 1 on the
LS148; (2) Pins 1, 2, 3, 4, 11, 12 and 13 (inputs 1, 2, 3, 4, 5, 6, 7) have a fan-in of 3
on the LS748 versus a fan-in of 2 on the LS148. The working can be clearly explained
with the help of functional table shown below.
Table 4.1 Truth table of Priority Encoders
By using Karnaugh map techniques, the above truth tables for both 10-line to
4-line (74LS147) and 8-line to 3-line (74LS148) priority encoder can be minimized
and the functional diagram consisting of various logic gates can be implemented as

shown in figure 4.1.
Figure 4.1 Functional Block Diagram
After designing the functional block diagram, various instances present inside
it are individually created and simulated in the analog design environment (ADE) to
verify the functionality and if the functionality roves to be correct finally the layout is
implemented. This chapter includes the various modules used in the design along with
the schematic, symbol, test circuit, layout and simulation results of each and every
block.
4.2 Logic gates
Digital systems are said to be constructed by using logic gates. These gates are
the AND, OR, NOT, NAND, NOR, EXOR and EXNOR gates. The basic operations
are described below with the aid of truth tables
4.2.1 AND gate
Figure 4.1 And gate symbol Table 4.1 And gate truth table
The AND gate is an electronic circuit that gives a high output (1) only if all its
inputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind

that this dot is sometimes omitted i.e. AB
4.2.2 OR gate
Figure 4.2 OR gate symbol Table 4.2 And gate truth table
The OR gate is an electronic circuit that gives a high output (1) if one or
more of its inputs are high. A plus (+) is used to show the OR operation.
4.2.3 NOT gate
Figure 4.3 NOT gate symbol Table 4.3 NOT gate truth table
The NOT gate is an electronic circuit that produces an inverted version of the
input at its output. It is also known as an inverter. If the input variable is A, the
inverted output is known as NOT A. This is also shown as A', or A with a bar over
the top, as shown at the outputs. The diagrams below show two ways that the NAND
logic gate can be configured to produce a NOT gate. It can also be done using NOR
logic gates in the same way.
4.2.4 NAND gate
Figure 4.4 NAND gate symbol Table 4.4 NAND gate truth table
This is a NOT-AND gate which is equal to an AND gate followed by a NOT
gate. The outputs of all NAND gates are high if any of the inputs are low. The
symbol is an AND gate with a small circle on the output. The small circle represents
inversion.
4.2.5 NOR gate

Figure 4.5 NOR gate symbol Table 4.5 NOR gate truth table
This is a NOT-OR gate which is equal to an OR gate followed by a NOT
gate. The outputs of all NOR gates are low if any of the inputs are high.
The symbol is an OR gate with a small circle on the output. The small circle
represents inversion.
4.2.6 EXOR gate
Figure 4.6 EXOR gate symbol Table 4.6 EXOR gate truth table
The 'Exclusive-OR' gate is a circuit which will give a high output if either,
but not both, of its two inputs are high. An encircled plus sign ( ) is used to show
the EOR operation.
4.2.7 EXNOR gate
Figure 4.7 EXNOR gate symbol Table 4.7 EXNOR gate truth table
The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will
give a low output if either, but not both, of its two inputs are high. The symbol is an
EXOR gate with a small circle on the output. The small circle represents inversion.
The NAND and NOR gates are called universal functions since with either
one the AND and OR functions and NOT can be generated.
4.3 Importance of layout
Layout is the process of creating an accurate physical representation of an
engineering drawing (may be a schematic or else the netlist) using the tools that

conforms to the constraints imposed by the manufacturing process, the design flow,
and the performance requirements shown to be feasible by simulation.
4.3.1 Automated layout
Automated process is the one with which the layout is done automatically just
by submitting the netlist to that tool.
It is much faster, and easy and less amount of tedious job for the layout
designer. But the disadvantage of using the automated process is that “it is not
intelligent”. Not intelligent in the view of some analog routing techniques and other
guidelines.
“MATCHING” cannot be obtained by using the automated process.
4.3.2 Custom layout
Custom layout is the manual layout done from the starting level. The layout
engineer has to take care of everything .i.e.,
• creating the devices
• doing floor plan,
• Take care of all the matching guidelines, routing and verification.
It is much tedious and slower job .But it is in the hands of the layout engineer
to take care of all the issues and other “MATCHING” guidelines. The process of the
layout starts from the input given by the design engineer .It can be a schematic for
analog design and can be the net list for the digital design.
4.4 Inputs from the designer
a) Schematic from the Circuit Designer
The Schematic mainly consists of the transistors symbol with the length and
width parameters of the transistor interconnected in various ways according to the
designer requirements.
• P-Transistor (High or Low Voltage).
• N-Transistor (High or Low Voltage).
• Resistors (Poly, Diffusion, Nwell, Metal resistors ).
• Capacitors (Moscaps, Poly-Metal, Metal-Metal Capacitors).
• Diode's (P-type , N-type Diode )
are the different devices that can be seen in the design.
b) Spice File
The spice netlist which contains the physical representation of the schematic

data which is required while doing Layout Vs Schematic check.
c) Matching Transistors
Designer will specify which transistors is to be matched, while doing layout .
For Example, The Differential Pair, Current Mirrors.
d) Current Densities
Designer will specify the current requirements if any net requires more than 1
mA of current. The widths of the nets which is specified by the Circuit Designer can
be calculated by using the current density calculations using Design Rule Document .
e) Critical Nets
The circuit designer will specify the High frequency nets which is to be taken
care by the layout designer while drawing the layouts. Critical nets should have less
parasitic and less routing length. These nets should not be routed near critical analog
signal like differential nets.
f) Matched Net
Circuit Designer will specify the nets, which should have to be matched
carefully. The layout Designer should match those nets such that both nets will face
same environment and should have same length.
For example, in OPAMP, the two input nets should not produce any
mismatches, because it will produce offset problems. So always try to provide the
same type of environment for those nets.
g) Guard rings
Generally the Guard rings are used for the isolation of the circuits, Sometimes
the Designer wants to isolate some sensitive transistor from other transistor, at that
time the schematic designer will specify the guard rings for those type of the
transistors. Sometimes the Layout designer will take decisions of placing the guard
rings without interference of the Designer, The situation like when there is a chance
of lot of noise to be penetrated in to the circuit.
“Guard rings minimize substrate resistance and reduce propagation of noise
in substrate, preventing latch up.”
4.5 From Foundry
a) Technology File

The technology file consists of the about layer definitions, tech layers, tech
layer purpose, tech displays, stream layers, and physical layers.
b) Display file
Display file mainly consists of the color display section where the color of
each layer is defined and display style section where the style for each layer to be
displayed is defined.
c) Rule files
There are three types of rule files available from any foundry to test the
design,
4.5.1 DRC
The design rule check step checks that all polygons and layers from the layout
database meet all of the manufacturing process rules. The design rules specify the
limits of a manufacturable design.
4.5.2 LVS
Layout versus Schematic checks the layout database whether it is in
accordance with schematic (netlist).
The Functions of the LVS are:
 Circuit Element Extraction.
 Electrical Node Extraction
 Layout Versus Schematic Check.
4.5.3 ERC
An electrical rule check is to be done to ensure that there are no short or open
connections in the design.
EXTRACTION: The extraction deck will extract the parasitic resistance and
capacitance of different nets from the layout.
4.6 Layers Classification
Layers may be the basic silicon layers, which form the basic devices, or may
be metal layer which define the interconnectivity between layer and devices.
• Conductors: They are capable of carrying signal voltages. Diffusion areas,
Metals and Polysilicon layers, and well layers fall into this category.
• Isolation Layers: They are present to provide isolation to avoid Short circuits
between separate electrical nodes. Example of isolation layers are dielectric layers
between the metal layers.

• Contacts or Via: These layers define cuts in the insulation layer that separate the
conducting layers and allow the contact down through the cut or contact hole.
• Implant layers: These layers do not explicitly define a new layer or contact, but
they will change existing conductor property.
• Device recognition layers: These layers do not contain any electrical
characteristics. As name implies these layers are used to identify different types of
devices. Mainly used by verification tools.
4.7 Analog Layout
4.7.1 Importance of Analog Layout:
Analog integrated circuits are very important as interfaces between the digital
parts of integrated electronic systems and the outside word. A large portion of the
effort involved in designing these circuits is spent in the layout phase, which
continues to be a manual, time-consuming and error-prone task. This is mainly due to
the continuous nature of analog signals, which causes analog circuit performance to
be very sensitive to layout parasitics. Successful automation of analog layout requires
a structured layout methodology, state-of-the-art CAD tools and a well-integrated
design system. In this chapter, we describe such a system and show its importance in
obtaining a manufacturable layout that meets all specifications at minimum cost and
in the minimum time. We give an overview of the advanced methods and tools
currently available for analog layout generation, migration and reuse.
4.8 Analog Vs Digital
Analog layout is usually done manually by circuit designer, but digital layout
is usually done automatically by CAD tools. For example in analog layout, the layout
of a NAND gate is done manually, but in digital layout, the layout of a NAND gate is
already in the CAD tool's library, and the CAD tool uses the different layout cells in
its library to construct the layout of a digital circuit usually designed using VHDL or
Verilog.
In analog layout the length of transistors is not usually the minimum, but in
digital it is. In analog layout matching of transistors is very important but it is not the
case in digital layout.
Transistor as switch in Digital Transistor as amplifier, resistor and other
passive in analog.
In Digital Layout, the W/L ratios used are the minimum feature size. This is

done to minimize the area and maximize the packing density. When the area is
minimized, the delay also gets minimised. Digital design is easier because we can use
cell-based methodology to do a layout, wherein you already have predefined layouts
of standard cells and use them to create larger blocks. This saves time and money.
Analog layout on the other hand is tougher as more importance is given to transistor
and interconnects details. This is done to achieve matching and the required currents
and voltages. Analog design is based mostly on the drain currents and bias voltages.
So, layout has to be done carefully to achieve these voltages and currents else the
design will fail when manufactured. In analog layout/design we trade off area for
performance.
4.9 Some of Important Analog Layout Guidelines
a) Don't Use Poly As Interconnect
In Digital designs the o/p is either high or low that is it can be either vdd or
gnd. But it is not the case in the analog design. Poly is a high resistive material so
using poly as interconnect can act as a resistive path to that sensitive signal in the
analog circuitry. Even this small voltage drop varies the ultimate o/p by a lot.
Metal1 high current density, poly very low current density
b) Don't Go For Minimum Metal Widths
By doing so, there may be the chance of breaks in the metal due to
manufacturing Deviations. The metal width determines the strength of the signal
that can be handled by it. Use more metal widths as the routing resistance
depends on the width of the metal through which it is routed.
Smaller metal width Larger metal width
Possibility of Open Possibility of open can be avoided
Using Metal As InterconnectUsing POLY As Interconnect
PreferredNot Preferred

c) Don't Go For Minimum Spacing
There may be chances of shorting of adjacent metals due to electro
migration (explained in coming chapters). The parasitic capacitance also increases
and there may be chances of coupling of two different signals that are running
parallel.
Minimum metal spacing Greater metal spacing
Parasitic cap.
d) Don't take power (vdd or vss) from Guard ring to MOS
For the flow of substrate noise in to the MOS transistor. Guard rings are use
to avoid LATCHUP. Taking power from guard rings has a larger no. of
disadvantages:
Source taking power from guard ring Guard ring (vdd)
i. Substrate noise always flow in the guard rings. So taking power from guard ring
has a chance
ii. Generally the metal width used for guard ring is very less. So it cannot support the
current
density required for the MOS transistor.
Source taking power from guard ring Source taking power from the vdd line
e) Use as many vias and contacts as possible
These are used wherever we want to jump from one metal layer to the other.
These are made of low resistance materials. Use at least more than one, as the number
increases the over all resistance at the point of jump reduces.
Possibility of signal coupling Possibility of signal coupling can
be avoided
VDD
vdd metal line
Not Preferred Preferred

VIA1'S
USING MORE NO OF VIAS
Smaller Value Resistance
EQ RES R = (R1*R2*R3*R4*R5*R6) /
(R1+R2+R3+R4+R5+R6)
USING LESS VIAS
larger the value of resistance to signal EQ RES R = (R1*R2) / (R1+R2)
f) It Is Always Better To Follow Metal Convention
Always prefer to use alternate metals in same direction. Using the different
metals without proper convention create problems in routing. In digital routing
without following the metal convention it is impossible to route complete block..
Avoid using jumpers for shorter length routing
g) Avoid Using Longer Routing Lengths :
Using longer lengths for routing increases the drop across the whole length of
the routing. And also it adds parasitic cap to that net.
“ The Longer the Length, the More is the Drop,
More is the Parasitic Cap.
h) Don't Chop Guard Ring For Routing
Chopping Guard ring for drain connection Separate metal connection
i) Don't Use Contacts And avoid Routing Over The Active Gate Area
The presence of contacts and routing over the active gate area increases the
Not Preferred Preferred

significant threshold voltage mismatches. As gate poly is very thin, there is a chance
that contact may penetrate in
To the gate oxide and routing may induce stress mismatches mainly to
matched pair. Even if leads need to be crossed over the active gate area they must be
maintained in symmetry.
This precaution will minimize the impact of metallization on matching but not
totally eliminate it. So for high precision matching one should entirely avoid routing
leads across the active gate regions.
j) Keep Deep Diffusions Away From The Active Gate Area
Deep diffusions can affect the matching of near by mos transistors. These
diffusions extend a considerable distance beyond their junctions, and the excess
dopant that they introduce can shift the threshold voltages and alter the
transconductanc of near by transistors.
k) Use Separate Power Supplies For Analog And Digital Blocks
Analog blocks are the very sensitive blocks where as the Digital blocks are
noisy. So always the analog blocks must be protected from the digital blocks.
1)Place the digital blocks completely away from the analog block so that the noise
from the digital block does not enter the sensitive side.
2)And use separate power supplies for both analog and digital. Using same power
supplies can affect the analog blocks because always there will be switching present
in the digital supply
l)Always Keep The Matched MOS Away From The Power Transistors
Power Transistors are those that uses a larger values of currents. Because they
carry huge amount of currents they dissipate more amount of heat (power dissipation
= i*i*R). The heat dissipated from the power device can extremely affect the matched
transistors. And proper protection is to be provided for the power transistor to absorb
that emitted heat.
Preferred Not Preferred

4.10 AND 2 input
Figure 4.8 2 input AND Schematic and layout
Figure 4.9 2 input AND symbol and test circuit
Figure 4.10 two input waveform

4.11 Not Gate
Figure 4.11 NOT Schematic and Layout
Figure 4.12 NOT Symbol and Test circuit
Figure 4.13 NOT Simulation waveforms

4.12 NOR 2 input
Figure 4.14 2 input NOR Schematic and Layout
Figure 4.15 2input NOR Symbol and Test circuit
Figure 4.16 2input NOR Simulation waveforms

4.13 NAND 2 input
Figure 4.17 2input NAND Schematic and Layout
Figure 4.18 2input NAND Symbol and Test circuit
Figure 4.19 2input NAND Simulation waveforms

4.14 AND 3 input
Figure 4.20 3input AND Schematic and Layout
Figure 4.21 3input AND Symbol and Test circuit
Figure 4.22 3input AND Simulation waveforms

4.15 AND 4 input

4.16 NOR 4 input
Figure 4.26 4input NOR Schematic and Layout
Figure 4.27 4input NOR Symbol and Test circuit

4.17 AND 5 input

4.18 NOR 5 input
Figure 4.32 5input NOR Schematic and Layout
Figure 4.33 5input nor Symbol and Test circuit

4.19 NAND 9 input
Figure 4.35 9input NAND Schematic and Layout
Figure 4.36 9input NAND Symbol and Test circuit
Figure 4.37 9input NAND Simulation waveforms

4.20 8x3 Priority Encoder
Figure 4.38 8x3 Priority Encoder Schematic and Layout
Figure 4.39 8x3 Priority Encoder Symbol and Test circuit

Figure 4.40 Priority Encoder Simulation waveforms without parasitics
Figure 4.41 8x3 Priority Encoder Simulation waveforms with parasitics

Figure 4.42 8x3 Priority Encoder with no DRC errors
Figure 4.43 8x3 Priority Encoder with no ERC errors
Figure 4.44 8x3 Priority Encoder with no LVS errors

Figure 4.45 8x3 Priority Encoder Layout with RC Extraction
4.21 10x4 Priority Encoder
Figure 4.46 10x4 Priority Encoder Symbol and Test circuit

Figure 4.47 10x4 Priority Encoder Schematic and Layout
Figure 4.48 10x4 Priority Encoder Simulation waveforms without parsitics

Figure 4.49 10x4 Priority Encoder Simulation waveforms with parasitics
Figure 4.50 10x4 Priority Encoder with no DRC errors
Figure 4.51 10x4 Priority Encoder with no ERC errors

Figure 4.52 10x4 Priority Encoder with no LVS errors
Figure 4.53 10x4 Priority Encoder Layout with RC Extraction

CHAPTER 5
CONCLUSIONS
An in-depth analysis of the individual logic circuits and their corresponding
simulation results was presented. Power consumption has a major impact on the
functionality and performance of a system. Various power optimization techniques
were used in order to reduce to overall power consumed by both the priority encoders.
A key challenge facing current and future computer designers is to reverse the
trend by removing layer after layer of complexity, opting instead for clean, robust,
and easily certifiable designs, while continuing to try to devise novel methods for
gaining performance and ease-of-use benefits from simpler circuits that can be readily
adapted to application requirements.
The project could not be accomplished without the use of Cadence EDA tools
that has to be attributed. It is the tools that accurately generated that results and its
easily modifiable graphical representation of the product proved advantageous. The
user can nearly view the actual product on screen, make any modifications to it,
and present his/her ideas onscreen without any prototype, especially during the early
stages of the design process.
Finally, the improved 10-line to 4-line and 8-line to 3-line circuits presented to
build the large systems, such as high performance microprocessors with low power
consumption. Through simulations results, we conclude that our new Priority
encoders consume considerably less power in the order of milli watts. With the help
of this priority encoder we can design efficient circuits that find its applications as in
elevators, winding machines, conveyors, etc. This kind of low power and high speed
priority encoders will be used in designing include detecting interrupts in
microprocessor applications and its applications in various fields. Its robustness
against transistor downsizing and voltage scaling allows the efficient power
optimization of noncritical signal nets and of entire circuit components.
It is the intention of this report to integrate these various topics and to provide
some sense of cohesiveness to the full custom design.

S.No Type
Typical data
delay(ns)
Typical power
dissipation(mW)
1
8X3 Priority encoder
(74LS148)
15 60
2
10X4 Priority encoder
(74LS147)
15 60
Table 5.1 Priority encoder TTL Design as per data sheet
5.1 Targets Achieved: Priority Encoder CMOS Design
S.No Specifications Priority Encoder
8x3
Priority Encoder
10x4
1 Technology 180nm 180nm
2 Supply 1.8v 1.8v
3 Area(µm) 62.26 x 283.15 76.97 x 279.2
4 Power without Parasitics (mW) 5.19 7.3125
5 Power with Parasitics (mW) 5.29 7.8866
6 Typical Data Delay(ns) 20 20
Table 5.2 Priority Encoder CMOS Design Target Achieved

REFERENCES
[1] Yusuf Leblebici, Sung-Mo Kang, CMOS Digital Integrated Circuits, McGraw-
Hill Ryerson Limited, 1996
[2] Jan M. Rabaey, Anantha P. Chandrakasan, Borivoje Nikolić, Digital Integrated
Circuits, 2/e, Pearson Education, 2003
[3] C.V.S Rao, Switching Theory and Logic Design, Dorling Kindersley (India)
Pvt.ltd, 2006.
[4] M. Morris Mano, Michael D. Ciletti, Digital Design, 4th Edition, Prentice Hall,
2006, ISBN 978-0-13-198924-5.
[5] Motorola.Inc, 10-Line-to 4-Line and 8-Line to 3-Line Priority Encoders [online].
Available: http://www.skot9000.com/ttl/datasheets/147.pdf.

APPENDIX
CADENCE OVERVIEW
Introduction
In this, we use the CADENCE to draw the schematic of two stage inverter
and test the circuit and plot its waveforms and find its propagation delay and power
dissipation and note it down draw its layout and check its layout using tools like
DRC, LVS, RCX and we generate the GDS file which is to be given to the fab city
from where the chip is designed. Some of the Tools used in cadence for our design
Schematics L
This is used to design the schematic of the circuit. It consists of in built
MOSFETS and for giving connection we make use of wires and after designing the
schematic we check and save the circuit and then we generate the symbol used for the
design of its test circuit of the schematics after designing its test circuit we will check
and save the circuit
Some of the short cuts used in schematic editor are
• [Press] i – It is used for generation of instances or components used in the design
of the circuit
• [Press] p – It is used for the generation of the pins which are used for giving
inputs and sources to the circuits
• [Press] w – It is used for generating wires, which are used for giving contacts
between the devices. It has two types of wires.
 Narrow
 Wide
We use this based on the requirements of the circuits
• [Press] f– It is used for fitting the circuit to its original circuits after zooming the
circuit
ADE L (Analog Design Environment)
This is used to run the circuit and plot its outputs and find the propagation
delay and power dissipation of the circuit and we can save the circuit state and
reload it whenever we use that circuit
Layout XL
This is used for designing the layout for the schematics. Some of the short cuts
used in this are:

• [Press] r – This is used for drawing rectangular layers
• [Press] shift + k– This is used for checking whether the required layer is
acquired with the desired length or not
• [Press] f – It is used for fitting the circuit to its original circuits after zooming the
circuit.
DRC: This is mainly used for checking whether the layout is designed
by following the design rules or not. It will notify the design rule violations, if any.
LVS: This is used to check whether the layout designed is exactly
matching with the schematics.
RCX: In this we can find the numbers of resistors and capacitors formed
due to the metal to metal contact and metal to poly contact
Design of Schematic
Initially open the terminal. We open the virtuoso tool by the path shown in the Figure
Figure A.1 Terminal window
Then virtuoso window will be opened along with the WHAT’S-New window.
Close what’s-new window. The virtuoso window:
Figure A.2 Virtuoso

Now go to FILE NEW LIBRARY Create a new library and enter its name
Figure A.3 New Library
Then attach an existing technology GPDK 180 to that library file. This
implies that all files related to 180nm technology are loaded to this library file.
Figure A.4 Technology Library
Figure A.5 New File
Figure A.6 Instance

Figure A.7 Instance Specifications
Then go to FILENEWCELL VIEW and enter its name and press OK
Then a new cell view will be opened.By pressing I, a new instance window will be
opened. Then click on the BROWSE a new window will be opened. Then click
on GPDK180.Then click on EVERY THING. Select NMOS and select its symbol
and click on OK.
The new instance window will be appeared, where we can edit the properties
of the NMOS.
Then click on Hide. Then NMOS symbol will be at the tip of the cursor
wherever you click on the screen there, you can obtain the NMOS. Then by using
wire we can give contact to all the remaining components.
Figure A.8 Schematic circuit
Then click on Check and Save Icon. This will check whether the given
circuit is designed without any errors and it will save the schematic.

Symbol Generation
Click on CreateCell view. Then a new window is opened. Click OK.
Figure A.9 Symbol Generation
Then another window is opened. Adjust pins positions
Figure A.10 Symbol Specification
Then the symbol is generated as:
Figure A.11 Symbol

Then click on Check and Save Icon .This will check whether the given
symbol is generated without any errors and it will save the schematic.
Schematic Simulation
Create a NEW CELL VIEW. Then press I it will open a instance window
from this select a VPULSE and its symbol edit its properties and place it on the newly
created cell view. Similarly select VDC, GND, and symbol of the schematic and
place them on the cell view. Make connections using wires and check and save
the test circuit generated.
Click on LAUNCHADE L.
Click on then a new CHOOSE ANALYSIS window will be open.
Click on tran.Set its stop time to 200nand click on then click on apply
Click on dcand click on and then click on apply.
Figure A.12 ADE Window
Figure A.13 Choosing Analyses
Then click on outputssave all

And click on
Then click on apply.
Figure A.14 Save Options
Then click on Outputs Outputs to be plotted. Select on test schematic
both input and output terminals. Then click on . Then the outputs will be plotted.
Figure A.15 Waveforms
Calculation of Propagation Delay
Click on Calculator. A new window will be opened. Click on

then on delay.
Click on Signal1and select the input from the output waveforms Click on
Signal2 and select the output from the output waveforms
Figure A.16 Calculation of Propagation Delay
Figure A.17 Calculation of Power Dissipation
Then click on append ( ). Then the propagation delay calculated will be
displayed on the screen

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