ECway Technologies provides IEEE projects and software development with offices across multiple cities in India. They offer 25 different 2013 IEEE VLSI project titles related to digital circuits, wireless communication, error correction, and signal processing. Project topics include glitch-free delay lines, low-power turbo decoders, multi-mode turbo/LDPC decoders, digital filters, asynchronous logic circuits, DSP architectures, ADCs, error correction for memories, random number generators, and low-power design techniques. ECway can be contacted through their website or phone numbers for more details on these projects.

1. ECWAY TECHNOLOGIES
IEEE PROJECTS & SOFTWARE DEVELOPMENTS
OUR OFFICES @ CHENNAI / TRICHY / KARUR / ERODE / MADURAI / SALEM / COIMBATORE
BANGALORE / HYDRABAD
CELL: +91 98949 17187, +91 875487 1111 / 2111 / 3111 / 4111 / 5111 / 6111 / 8111
Visit: www.ecwayprojects.com Mail to: ecwaytechnologies@gmail.com
S.N.
2013 IEEE VLSI PROJECT TITLES
1.
Glitch-Free NAND-Based Digitally Controlled Delay-Lines
2.
A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless
Sensor Networks
3.
VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture
4.
Broadside and Skewed-Load Tests Under Primary Input Constraints
5.
Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density
Parity Check (EG-LDPC) Codes
6.
Efficient Implementation of Reconfigurable Warped Digital Filters With
Variable Low-Pass, High-Pass, Band pass, and Band stop Responses
7.
Eliminating Synchronization Latency Using Sequenced Latching
8.
Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits
9.
Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes
10.
Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using
Polynomial Fitting Measurements
11.
Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment

2. 12.
Reducing the Cost of Implementing Error Correction Codes in Content
Addressable Memories
13.
The LUT-SR Family of Uniform Random Number Generators for FPGA
Architectures
14.
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization
15.
Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data
Priority
16.
Static Power Reduction Using Variation-Tolerant and Reconfigurable MultiMode Power Switches
17.
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low
Adaptation-Delay
18.
Configurable ring oscillator with physically un clonable frequency based
random number generation
19.
Eliminating Synchronization Latency Using Sequenced Latching
20.
VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture
21.
Smart Reliable Network-on-Chip
22.
Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes
23.
A Reconfigurable Direct RF Receiver With Jitter Analysis and Applications
24.
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
25.
Built-In Generation of Functional Broadside Tests Using a Fixed Hardware
Structure