1. 3.3 Computer Architectures
3.3 Computer Architectures 1

2. 3.3 Computer Architectures
a) Describe the classic Von Neumann architecture, identifying the need
for, and the uses of, special registers in the functioning of a processor
b) Describe in simple terms the fetch/decode/execute cycle
and the effects of stages of the cycle on specific registers
c) Discuss co-processor, parallel processor and array processor
systems, their uses, advantages and disadvantages
d) Describe and distinguish between Reduced Instruction Set
Computer (RISC) and Complex instruction Set Computer
(CISC) architectures
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3. Von Nuemann
a) Describe the classic Von Neumann architecture, identifying the
need for, and the uses of, special registers in the functioning of a
processor
b) Describe in simple terms the fetch/decode/execute cycle and the
effects of stages of the cycle on specific registers
1. Single processor architecture
2. Identify the special registers involved in the functioning of the
processor
3. Describe the fetch – decode – execute cycle
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4. John Von Neumann
In early computers data and programs were stored in separate
memories. Von Neumann realised that there is no need for this as
they are indistinguishable when it comes to storing – thus data and
programs can be stored in the same memory.
The Von Neumann architecture:
• Uses a single processor for program control
• that follows the fetch – decode – execute
• Execution is performed one instruction at a time in a linear sequence
• A single memory is used to store program instructions and the data for
use with the instructions
 Suitable for use when certain steps in an algorithm have to be done in
order
 As there is only one processor this is ‘time hungry’
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5. The registers
A register is simply an area of the processor that stores specific data.
There are several special registers that play a very specific role in
regarding the fetch – decode – execute cycle
Register Purpose
PC – program counter Holds the address of the next instruction to be
carried out
CIR - current instruction register Holds the instruction that is being executed as it is
being carried out
MAR – memory address register Holds the address in memory that is currently
being used
MDR – memory data register Holds the data or instructions that is being stored
in the address accessed by the MAR
Accumulator Holds results of processing
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6. Central Processing Unit
Main memory
00001
Control Unit
00011 ALU
PC
01010 Accumulator
00101
CIR
00010
00011
00100 01100111 MAR
00110 7
MDR 00100110
00111 12
Above is a recap from unit 1. The arrows represent the flow of data/instructions
1. The ALU is where data is processed – particularly arithmetic and logic operations
2. The control unit fetches instructions from memory and decodes them making use of other parts
of the computer as well
3. The accumulator is in the ALU and is where results of data processing is stored within the ALU
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7. Von Neumann - Questions
Q1 One feature of Von Neumann architecture is the use of the fetch-execute
cycle. State TWO other features of Von Neumann architecture.
1. single control unit/processor manages program control
2. program stored with data… in the same format… in the same memory
3. Execution is performed one instruction at a time
Q2 Explain what is meant by the Von Neumann Architecture
1. A single processor is used which follows a linear sequence of instructions
2. A single memory is used to store program instructions and the data for use with the instructions
Q3The program counter is a special register in the processor of a computer.
Describe the function of the program counter
1. The program counter stores the address
2. Of the next instruction to be carried out in the sequence of the program
Q4 Give the names of THREE other registers used by the processor.
(Do not use abbreviations)
1. Memory address register
2. Memory Data register
3. Current instruction register
4. Accumulator
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8. Fetch – Decode - Execute
b) Describe in simple terms the fetch/decode/execute cycle and the
effects of stages of the cycle on specific registers
1. Describe the fetch – decode – execute cycle including the
use of registers
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9. Fetch –Decode - Execute
Processing within the Von Nuemann architecture is carried out
using the fetch – decode – execute cycle.
Fetch: The instruction is „fetched‟ ready for processing
Decode: the instruction is divided up into the operation part and
data part and interpreted
Execute: The instruction is executed
You need to understand how each step works in detail.
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10. Fetch
1. The PC holds the address of the next instruction to be carried out
2. When the next instruction is needed it‟s address is copied from the PC
and placed in the memory address register
3. The PC is incremented by the program loader so it points to the next
instruction
4. The address is found in memory and the contents are placed in the
memory data register
5. The contents of the MDR are then copied to the CIR ready for the next
stage
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11. Fetch
Central Processing Unit
Main memory
00001
Control Unit
00011
ALU
PC 00101
00100
01010
Accumulator
00101 00100110
CIR
00010
00011
00100 01100111 MAR
00110 7
00111
MDR 00100110
1. A program loader places the addresses of instructions to be processed into the PC (program counter)
2. The PC stores and points to the address of the next instruction to be carried out
3. When the next instruction is needed it’s address is copied from the PC and placed in the MAR
4. The PC is incremented so it points to the next instruction
5. The address in the MAR is found in memory and the contents are placed in the memory data register
6. The contents of the MDR are then copied to the CIR ready for the next stage
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12. Decode
• The instruction in the CIR is split into its individual parts e.g
operation code (e.g add) and the address of the data
involved
• The address is placed in the MAR and the data goes in the
MDR
• The control unit „decodes‟ the operation code so the processor
knows what to do
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13. Decode
Central Processing Unit
Main memory
00001 Control Unit
00011 ALU
PC 00100
01010 Accumulator
00101 001 00110
CIR
00010
00011
00100 01100111 MAR
00110 7
MDR 00100110
00111 12
1. The instruction in the CIR is split into its individual parts e.g operation code (e.g add) and the address of the
data involved
2. The address is placed in the MAR and the data goes in the MDR
3. The control unit ‘decodes’ the operation code so the processor knows what to do
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14. Execute
In this stage the instruction is executed which could mean it needs to:
• Perform a logical/arithmetic based instruction – using the accumulator
• Execute a JUMP instruction
Arithmetic/Logic instructions:
• These will be sent to the ALU to be processed. The results will be stored in the
accumulator
JUMP instructions:
Sometimes an instruction will tell the computer to JUMP to another instruction
rather than just progress to the next instruction in a program (Think about your
different selection statements.) A jump instruction will tell the CPU the address of
the new instruction so it can then go and fetch it.
More about this on the next slide
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15. Jump instructions
JUMP instructions:
Imagine we had the instructions 1,2, 3, 4, 5, 6 etc. The computer would normally
start at instruction 1 and then go to instruction 2 etc
There could be a case where instruction 2 says to JUMP straight to instruction 5
(thus missing out instructions 3 & 4) This is called a JUMP instruction
What
A JUMP instruction tells the CPU to jump to a specific instruction out of sequence
How a JUMP instruction works
It will tell the CPU the address of the new instruction is stored so it can then go and
fetch it. To do this it:
1. The address part of the instruction from the CIR is copied into the PC
2. This means the address in the PC is the address of the new instruction
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16. Jump Instruction
When the jump Central Processing Unit
instruction is being
executed:
Control Unit
The address part of the ALU
PC 00100
instruction from the CIR Accumulator
is copied into the PC
CIR 001 00110
This means the address
in the PC is the address
of the new instruction
MAR
MDR 00100110
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17. Fetch – Decode – Execute: Putting the stages together
Fetch – decode – execute cycle:
1. Address of the next instruction is stored in the PC
2. Contents of the program counter are loaded into the MAR (memory address register)
3. The PC is incremented (to point to the next instruction)
4. Contents of addresses stored in MAR loaded into MDR (memory data register)
5. Contents of MDR loaded into CIR
6. The instruction in the CIR is divided into address of the data and the operation to be
performed
7. If the instruction is a jump instruction, load the new instruction address into the PC and go
back to step one
8. If it is a „normal‟ instruction the data is found using (the address in the MAR) and placed
in the MDR and the instruction is executed and control returns to step 1
Steps 1 – 5 = fetch Step 6 = decode Step 7 – 8 execute
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18. Summary
Von Neumann architecture:
• Uses a single processor for program control
• that follows the fetch – decode – execute
• Execution is performed one instruction at a time in a linear sequence
• A single memory is used to store program instructions and the data for use with the
instructions
Registers
• The PC (program counter) stores the address of the next instruction to be executed
• The MAR holds the address in memory that is currently be used
• The MDR holds the data or instructions that is stored in the address currently in the
MAR
• Current instruction register holds the instruction currently being executed.
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19. Summary
Fetch decode execute:
1. PC holds address of next instruction
2. Copy contents of PC to MAR
3. Increment PC
4. Contents of the address stored in MAR loaded into MDR
5. Copy instruction from MDR to CIR
6. Decode instruction in CIR
7. Execute instruction
this may involve;
a jump in which case a new address is placed in the PC
An arithmetic or logical expression in which case the ALU
and accumulator are involved
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20. Fetch – Decode – Execute Questions
Q1 The program counter is a special register in the processor of a computer.
Describe the initial state of the program counter before the running of the
program [2]
1. The PC will contain the address of the first instruction in the sequence to be run
2. This will have been placed in the register by some external agent called the program loader
Q2 Describe 2 ways in which the program counter can change during the normal
execution of a program, explaining, in each case, how this change is initiated [4]
1. The PC is incremented .......
2. As part of the standard flow of the fetch – execute – cycle
1. When the current instruction says to JUMP to another instruction out of sequence.....
2. The ‘jump to’ address in the CIR is placed into the PC and the associated instruction is executed
Q3 Describe how a jump instruction is executed. [2]
1. changes the contents of PC to address of the new instruction that is being jumped to
2. By copying the ‘jump to’ address part of instruction currently
3. in the CIR to PC
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21. Fetch – Decode – Execute Questions
Q4 Describe the fetch-execute cycle. [4]
1. PC holds address of next instruction
2. copy contents of PC to MAR
3. increment PC
4. Contents of address stored in MAR loaded into MDR
5. copy instruction from MDR to CIR
6. decode instruction in CIR
Q5 Describe the fetch – decode part of the fetch/decode/execute cycle,
explaining the purpose of any special registers that you have mentioned [7]
1. Contents of the PC loaded into MAR
2. PC is incremented
3. Contents of address stored in MAR loaded into MDR
4. copy instruction from MDR to CIR
5. decode instruction in CIR
6. PC stores the address of the next instruction to be executed
7. MAR holds the address in memory that is currently being used
8. MDR holds the data or instruction that is being stored in the address accessed by the MAR
9. CIR holds the instruction which is currently being executed
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22. Other computer Architectures
c) Discuss co-processor, parallel processor and array processor systems, their uses,
advantages and disadvantages
Not all computers have one processor working in a linear fashion. It
would make sense to try and deal with multiple instructions at the
same time. The following architectures aim to do this:
1. Co-processor
2. Parallel processor
3. Array processor
4. Pipelining
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23. Co-processors
What is a co-processor?
This is an additional processor used for a specific task such as mathematical
processes.
They improve processing speed by executing concurrently (at the same time)
with the main processor.
• eg maths co-processor
Main processor CO- PROCESSOR
(maths)
I can do all tasks I just do maths
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24. Pipelining
Using the fetch – decode – execute cycle it should be apparent that an
instruction can be in any one of 3 phases.
Pipelining: We can split the processor up into 3 parts each of which
handles one of the 3 stages.
This means more than one instruction can be dealt with simultaneously.
This results in the situation shown in below which is referred to as
‘pipelining’.
Fetch Decode Execute
Instruction 1 A static representation
Pipelining works providing
Instruction 2 Instruction 1
the next instruction in the
pipeline is the next one to
Instruction 3 Instruction 2 Instruction 1 be executed. Lets see what
happens if there is a JUMP
Instruction 4 Instruction 3 Instruction 2 instruction
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25. Pipelining and JUMP instructions
Imagine instruction 2 is a jump to instruction 10. Then instruction 3, 4, and
5 need to be removed from the pipeline and instruction 10 needs to be
loaded into the fetch part of the pipe – The pipeline must be RESET.
Normal Flow Jump Instruction Flow
Fetch Decode Execute Fetch Decode Execute
Instruction 1 Instruction 1
Instruction 2 Instruction 1 Instruction 2 Instruction 1
Instruction 3 Instruction 2 Instruction 1 Instruction 3 Instruction 2 Instruction 1
Instruction 4 Instruction 3 Instruction 2 Instruction 4 Instruction 3 Instruction 2
Instruction 5 Instruction 4 Instruction 3 Instruction 10
If instruction 2 says jump to instruction 10. Then Instruction 11 Instruction 10
the instructions in the pipeline are no longer
the ones to be dealt with next thus the pipe
must be reset and the new instruction placed Instruction 12 Instruction 11 Instruction 10
at the beginning
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26. Parallel Processing
Parallel processing architecture:
1. Uses multiple processors
2. Controlled by a complex OS
3. To work on different tasks within the same job at the same time
4. Each processor gets a DIFFERENT task
5. Which can greatly speed up processes e.g arithmetic ones
Advantages
Can deal with multiple inputs at the same time and process them all
simultaneously eg weather stations.
Disadvantages
In order to get the full benefits of Parallel processing programs need to have been
specifically written for them.
If a program has been designed for a single processor architecture than some
complex processing will be required to adapt the sequential algorithm As you
may not be able to process instruction 20 unless instructions 1-19 have been
processed first.
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27. Array Processing
This involves one processor but MULTIPLE ALUs.
An array processor is able to do the same calculation on multiple data
locations(rather than starting at the beginning and processing them one
by one.). This speeds up processing.
SIMD – Same instruction multiple data
This is useful for things like weather forecasting
1 2 3 4 5 6 7
45 66 87 34 23 5 66
Eg. process = Index i * 17.5%
ALU 1 ALU 2 ALU 3 ALU 4 ALU 5 ALU 6 ALU 7
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28. Architectures Summary
Von Neumann
• Uses a single processor that follows a linear sequence of fetch – decode –
execute
• Uses special registers to store different data
• Instructions and associated data are stored together in the same memory
 Effective when the result of an algorithm is dependent on the order in which
the steps are taken. E.g a formula
 Is time hungry as only one instruction is executed at a time
Co Processor
An additional processor used for a specific task such as mathematical processes.
They improve processing speed by executing concurrently (at the same time)
with the main processor.
Not quite as versatile as a parallel processor as the co - processor can only
perform specific jobs
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29. Architectures Summary
Pipelining
• Where the CPU is divided into 3 areas to handle the fetch, decode and
execute stages of processing an instruction.
• Each part can hold a different instruction so more than one instruction can be
dealt with simultaneously
Disadvantage
The pipeline will need to be reset if there was a JUMP instruction as there
instructions backed up in the pipeline will no longer be the next ones to be
executed.
Array Processor
This involves one processor but MULTIPLE ALUs.
An array processor is able to do the same calculation on a range of memory
locations simultaneously
e.g performing the same processing on each item of data in an array
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30. Architectures Summary
Parallel Processor
Has multiple processors (compared to Von Neumann which has just 1)
1. Uses multiple processors
2. Controlled by a complex OS
3. To work on different tasks within the same job
4. at the same time
5. Each processor gets a different task
Advantages
• Can deal with multiple inputs at the same time and process them all simultaneously eg
weather stations thus speeds up processing
• Complex tasks can be dealt with efficiently
Disadvantages
• In order to get the full benefits of Parallel processing programs need to have been
specifically written for them.
• Not suitable for some programs designed to be executed in a linear fashion
Computer architectures could potentially be a long question. Make sure you know
about each different sort of architecture in detail.
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31. Alternative Computer architectures - Questions
Q1 In some computer systems, a co-processor may be used. State what is meant
by a co-processor
1. an additional processor
2. used for a specific task
3. improves processing speed by executing concurrently
4. Eg maths co-processor/floating point accelerator
Q2 Describe how pipelining normally speeds up the processing done by a
computer [2]
1. All instructions have 3 stages (fetch-decide-execute)
2. We can split the processor up into 3 each of which handles one of the 3 stages.
3. This means more than one instruction can be dealt with simultaneously.
Q3 State one type of instruction that would cause the pipeline system to be reset,
explaining why such a reset is necessary [3]
1. A jump instruction
2. The instructions in the pipeline are no longer the ones to be dealt with next
3. So the pipeline has to be reset
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32. Alternative Computer architectures - Questions
Q4 Explain, with the aid of an example, the following statement “ A co-processor
is a simple form of parallel processor” [2]
• It is an additional processor alongside the central processor
• improves speed by performing specific tasks concurrently with central processor a bit
like how parallel processors can work at the same time
• However the co-processor can only deal with certain types of jobs so it is not as flexible
as the pp system e.g. maths co-processor/floating-point accelerator.
Q5 Describe parallel processing [5]
1. More than one processor…
2. …controlled by a complex operating system
3. working simultaneously…
4. to perform a single job…
5. which is split into tasks…
6. each task may be performed by any processor.
Q6 Describe one advantage and one disadvantage of a parallel processor
compared with a single processor system [2]
 Increased processing speed as multiple instructions are being processed at once
 Complex tasks can be performed efficiently
 Not suitable for some programs designed to be executed in a linear fashion
 To maximise efficiency programs need to be specially designed with multiple processors in mind
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33. Alternative Computer architectures - Questions
Q7 Explain the use of an array processor
An array processor is able to do the same calculation on a range of memory locations
simultaneously
As it is performing lots of calculations at the same time it is very fast
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34. RISC and CISC
d) Describe and distinguish between Reduced Instruction Set Computer (RISC) and
Complex instruction Set Computer (CISC) architectures
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35. RISC: restricted instruction set computers
The number of instructions recognised by a computer is limited. The more
operations a computer can recognise the more ‘bits’ are needed for it’s
operation set. In our earlier example of machine code had the following
operation table:
000 Divide one number by the new number Think about the instructions a calculator
might understand compared to a full PC.
001 Add two numbers together
010 Subtract one number from another
011 Input a number from the outside
100 Output a value
101 Store a number in a memory location
110 Get a value from a memory location
B
There are two categories of processors that vary in their operation sets:
CISC – Complex instruction set computers
RISC – Restricted/reduced instruction set computers
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36. RISC / CISC
Both use one or more register sets but have their own characteristics as
well
CISC: These have operation codes for all the operations they have to do
e.g they could have 1000s of different opcodes
They have MANY addressing modes
RISC: The number of operations recognised by this computer is limited.
Thus the number of bits needed to represent an instruction is reduced,
hence saving space within the CPU.
It doesn’t mean they cannot do as many operations it just means
‘missing’ instructions have to be made up from the ones that are
available. Which makes slower processing than CISC
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37. Efficiency of RISC and CISC
RISC only has a simple instruction set thus to
perform a complex task it may take several
„cycles‟ of basic instructions.
CISC has more complex instructions available
to it thus it may be able to perform the task in
just one cycle (by using one of its complex
operations available)
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38. Example of cycles
A RISC might have the operations: A CISC might have the operations:
• ADD • ADD
• SUB • SUB
• DIV • DIV
• etc • AVR (average)
• etc
If an instruction was sent to find the average of the numbers 5, 6, 7, 2, 3
the CISC system could use it’s AVR operation
whereas the RISC system would need to perform the same tasks but by
using it‟s ADD and DIV instructions (which means more cycles of
instructions)
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39. RISC
Reduced Instruction Set Computer
Limited number of instructions available
Number of bits required to store the whole instruction set is
small.
Can perform more complex instructions by executing
several cycles of simple instructions
As a result might work slightly slower than a CISC system
use one or more register sets
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40. CISC
Complex Instruction Set Computer
Large number of instructions available to use
Requires a larger number of bits than RISC to store the
larger set of instructions
They have many addressing modes
use one or more register sets
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41. WARNING
NEVER say RISC systems cannot do as
many operations as CISCs systems, as
this is NOT true.
They many just take several more cycles
to perform the same complex task.
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42. RISC / CISC
Q1 What does RISC stand for
Restricted Instruction set computer
Q2 What does CISC stand for
Complex Instruction set computer
Q3 Explain what is meant by a Reduced Instruction Set Computer architecture
and how it differs from a Complex Instruction Set Computer
1. In order to reduce the number of bits needed to represent an instruction code
2. The number of operations recognised by a RISC computer is limited
3. Complex instructions can still be created by using the available operations in
combination
4. This makes processing slower than in a CISC which has more standard operations
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