1. Ex No :1a
DESIGN & SIMULATION OF COMBINATIONAL LOGIC CIRCUITS
(Structural modeling)Date :
AIM:
To Design the following Combinational Circuits using verilog HDL and Simulate using Xilinx
foundation Series ISE version9.1
a) Half Adders
b) Full adder
c) Parallel adder
d) Multiplexer
e) Demultiplexer
f) 2-bit Magnitude Comparator
TOOLS REQUIRED:
Simulation Tool: Xilinx ISE 9.1 Simulator
DESIGN:
a) Half adder
Circuit Diagram& Truth Table
1

2. A & B- Inputs
S-Sum
C-Carry
Verilog Module
Output Waveform
2
TRUTH TABLE
Input Output
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

3. b) Full Adder
Circuit Diagram& Truth Table
A & B- Inputs
Ci-Input Carry
S-Sum
Co-Output Carry
Verilog Module
i) Without Instantiation
3
TRUTH TABLE
Input Output
A B Cin Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

4. ii) With Instantiation
4

5. Output Waveform
c) Parallel Adder
Circuit Diagram
5

6. A3 A2 A1 A0 &
B3 B2 B1 B0 are
operands.
C0- input carry
C4 -output carry
S3 S2 S1 S0-Sum
Verilog Module
Output Data
d) Multiplexer
Circuit Diagram & Truth Table
6

7. S0S1-Select Lines
D0 D1 D2 D3- Input variable
X- Output
Verilog Module
Output waveform
7
TRUTH TABLE
Inputs Output
S0 S1 X
0 0 D0
0 1 D1
1 0 D2
1 1 D3

8. e) De-multiplexer
Circuit Diagram & Truth Table
S0S1-Select Lines
Inp- input
O0 O1 O2 O3- Output
Verilog Module
8

9. Output Waveform
f) Two- bit Magnitude Comparator
Circuit Diagram
Verilog Module
9

10. Output Wave form
PROCEDURE:
i) Open the application software Xilinx window.
ii) Open a new project
a). Give the project name, check for configuration ‘Spartan 3E’ in next window.
b). Open new source verilog module, give the file name.
c). Give the name for input and output variables of the program.
d). Click Finish.
iii) Type the program to be synthesized.
iv) Save the program.
v) Run the synthesis tool.
vi) After completion of successful synthesis, click and view the RTL schematic.
vii) RTL schematic view window is open and synthesized circuit is seen on the screen.
10

11. VIVA QUESTIONS:
1. What are Min val & Max val Specifications in Gate Level Modeling?
2. What is Wire
3. Give the Verilog Data types?
4. What is Hardware Description Language
5. Give the Different types of modeling. Arrange them in descending order from highest
level of abstraction to lowest
RESULT:
11
Preparation /40
Output & Result /30
Viva /30
Total /100