1. Functional Verification of
CAN Controller
A.N.S.S.Prasad
Under the Guidance of
Mrs. Jayagowri.R
Vellore Institute of Technology

2. Verification of CAN Cotroller206/18/15
Outline
• Myths
• Facts and Figures
• What is verified
• How it is verified - Reconvergence Model
• Functional Verification Approaches
• Verification Plan
• Verification Components Created
• Test Categories Identified
• Results
• Conclusions and Future work

3. Verification of CAN Cotroller306/18/15
Myths
• Verification is a testbench
• Verification work starts only after
design is complete
• Verification and Design are
independent
• Design is more complex and
challenging than verification

4. Verification of CAN Cotroller406/18/15
Facts and Figures
• 60-80% of effort in Hardware Design goes
for Verification
• No. of Verification engineers = (2 or 3) * No.
of RTL engineers
• The code that implements the testbenches
makes up to 80% of total code volume
• Verification - a bottle neck in the ASIC
design flow

5. Verification of CAN Cotroller506/18/15
CAN Overview
• What is CAN?
• Why CAN?
• CAN Features
– Message Framing
– Arbitration
– CRC Generation
– Stuffing and Destuffing
– Error Detection and Signaling
– Fault Confinement
– Acceptance Filtering
– Overload Notification

6. Verification of CAN Cotroller606/18/15
Verification Goals
• To design and develop a flexible and user
friendly verification environment which is
portable over different design
implementations
• To provide for ease of error analysis and
redesign
• To verify that the design is functionally in
accordance with the CAN Specification 2.0

7. Verification of CAN Cotroller706/18/15
Reconvergence Model
Specification
Interpretation
Interpretation
RTL
Coding
Verification

8. Verification of CAN Cotroller806/18/15
Functional Verification
Approaches
• Black Box Verification
• White Box Verification
• Grey Box Verification
•Portability
•Controllability
•Visibility

9. Verification of CAN Cotroller906/18/15
Verification Plan
• A specification for verification effort
• Defines
– How a design is verified
– Which test bench components are created
– How complex they need to be - functionality
– How they depend on each other
– Test Categories
– Test Cases and their priority

10. Verification of CAN Cotroller1006/18/15
Verification Strategy
• Use of both white box and black box
test cases
• The test cases shall be specified at a
higher level of abstraction
• Completely automated test cases
• Randomization of content

11. Verification of CAN Cotroller1106/18/15
Verification Components
• Test Case - TC
• Microcontroller Emulator – MCU-EMU
• CAN node Emulator - CAN-EMU
• Response Checker - RC
• Bus Functional Model - BFM

12. Verification of CAN Cotroller1206/18/15
Verification Environment
CAN Bus
Functional
Model
(BUS-EMU)
CAN Node
Emulator 1
(CAN-EMU)
DUV Tx
DUV Rx
CAN Tx
BFM_MD
CS#
INT#
WRL#
CLK
WRH#
Addr[7:0]
Data[15:0]
CAN
Controller
Device (DUV)
Micro
controller
Emulator
(MCU-EMU)
RD#
RST#
Test Cases
Response
Checker
CAN Rx

13. Verification of CAN Cotroller1306/18/15
Client Server Protocol
Abstraction
Client
process
Server Process
Client Procedure Server Procedure

14. Verification of CAN Cotroller1406/18/15
Test Case
• Triggers Emulators
and Checkers
• Sets up the
scenario
• No ports
• Procedures
– MAK_TMO
– MAK_STND_ID
– MAK_EXTD_ID
– MAK_DATA

15. Verification of CAN Cotroller1506/18/15
MCU-EMU Interface
CS#
INT#
WRL#
CLK
WRH#
Addr[7:0]
Data[15:0]
CAN
Controller
Device (DUV)
Micro
controller
Emulator
(MCU-EMU)
RD#
RST#
• Configures the
DUV
• Controls the DUV
• Runs at a
programmable
frequency
• Checks RMOs
(Receive
Message Objects)

16. Verification of CAN Cotroller1606/18/15
MCU-EMU
• Procedures
– RD_REG
– WR_REG
– CFG_ACC_FLTR
– CFG_TIM_PARAM
– RD_MSG_OBJ
– WR_MSG_OBJ
• Records
– Mcu_emu_ctrls_rec
– From_mcu_rec
– Msg_obj_rec

17. Verification of CAN Cotroller1706/18/15
CAN-EMU
• Behaves like a CAN node or a
behavioral model of DUV
• Transmits messages to the DUV
• Injects errors into the environment
• Controls the BFM’s mode of operation

18. Verification of CAN Cotroller1806/18/15
CAN-EMU
• Procedures
– TX_FRM
– RX_FRM
– FRM_BLD
– CRC_GEN
– CRC_INP_GEN
• Records
– Can_emu_ctrls_rec
– Msg_obj_rec
– Tim_params_rec
– Err_info_rec

19. Verification of CAN Cotroller1906/18/15
BFM
• Operates in two modes
– Control mode
– Normal mode
• Emulates programmable delays
• Provides interface to a programmable
number of CAN nodes
• Controlled by CAN-EMU through TC

20. Verification of CAN Cotroller2006/18/15
Response Checker
• Generates expected response of the
DUV
• Compares expected response and
received response
• Bit timing parameters same as that of
DUV

21. Verification of CAN Cotroller2106/18/15
Response Checker
• Procedures
– RSP_BLD
– FRM_BLD
– STRT_CHK
• Records
– Rsp_chkr_ctrls_rec
– Msg_obj_rec
– Tim_params_rec
– Err_info_rec

22. Verification of CAN Cotroller2206/18/15
Test Cases
S.N
o
Test
Case ID
Test Description Expected Behavior
1 BAS-
1000
The DUV is loaded with dominant
RTR and dominant IDE bits to make
a Standard Format Data Frame.
Other fields no bar.
The DUV is expected to transmit a
Standard Format Data Frame in
conformance with the CAN
Specification 2.0
2 BAS-
1001
The DUV is loaded with recessive
RTR and dominant IDE bits to make
a Standard Format Remote Frame.
Other fields no bar.
The DUV is expected to transmit a
Standard Format Remote Frame in
conformance with the CAN
Specification 2.0
3 BAS-
1002
The DUV is loaded with dominant
RTR and recessive IDE bits to make
a Standard Format Remote Frame.
Other fields no bar.
The DUV is expected to transmit an
Extended Format Data Frame in
conformance with the CAN
Specification 2.0
4 BAS-
1003
The DUV is loaded with recessive
RTR and recessive IDE bits to make
a Standard Format Remote Frame.
Other fields no bar.
The DUV is expected to transmit an
Extended Format Remote Frame in
conformance with the CAN
Specification 2.0
1400

23. Verification of CAN Cotroller2306/18/15
Conclusions and Future work
• A user friendly and portable
verification environment is created
• The test cases can be run using
scripts
• Code coverage metrics can be used
to assess the verification
completeness

24. Verification of CAN Cotroller2406/18/15
Reset Tests

25. Verification of CAN Cotroller2506/18/15
Interface Tests

26. Verification of CAN Cotroller2606/18/15
Message Framing Tests

27. Verification of CAN Cotroller2706/18/15
Acknowledgement Tests

28. Verification of CAN Cotroller2806/18/15
Arbitration Tests

29. Verification of CAN Cotroller2906/18/15
Error Detection and signaling

30. Verification of CAN Cotroller3006/18/15
Overload Notification Tests

31. Verification of CAN Cotroller3106/18/15
References
• Writing testbenches Functional verification of HDL
models by Janick Bergeron KAP publishers
• CAN Specification 2.0 Part A,B
• High Level Design Document of CAN Controller
Device Revision 0.3
• International Technology Roadmap for
Semiconductors 2005
• Motorola Semiconductor Application Note – AN1798
• Microchip Application Note – AN713
• Controller Area Network CAN A Serial Bus System – Not Just For
Vehicles esd gmbh Hannover

32. Verification of CAN Cotroller3206/18/15
Questions

33. Verification of CAN Cotroller3306/18/15
CAN Network

34. Verification of CAN Cotroller3406/18/15
Message Frame Format

35. Verification of CAN Cotroller3506/18/15
Arbitration

36. Verification of CAN Cotroller3606/18/15
Test Categories
• Message framing
• Arbitration
• Acknowledgement
• Stuffing and
Destuffing
• Error detection and
signaling
• Fault confinement
• Acceptance Filtering
• Overload notification
• Interrupt
• Performance
• Reset
• Interface
• Bit Timing

37. Verification of CAN Cotroller3706/18/15
Procedures and Records
• Framing
• Stuffing
• Response Building
• Random no.
generation
• CRC generation
• Configure Timing
• Message frame
• Frame components
• Error info
• Register
• Checker controls
• Loaded frame
components
• Received frame
components

38. Verification of CAN Cotroller3806/18/15
Examples
RD_RG(acc_cd2_reg,to_mcu.reed);
wait on from_mcu.reed'transaction;
WR_RG(acc_cd1_reg,X"ABCD",to_mcu.rite,wr_16
_bit);
wait on from_mcu.rite'transaction;

39. Verification of CAN Cotroller3906/18/15
Examples
type msg_obj_rec is
record
id :std_logic_vector(28 downto 0);
--Identifier
frm_type :frm_typ_typ; --RTR
frm_frmt :frm_frmt_typ; --IDE
dat_len :std_logic_vector(3 downto 0); --DLC
data :std_logic_vector(63 downto 0); --Data
end record msg_obj_rec;