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Lecture :

               TRANSISTOR BIAS
                   CIRCUITS
Code:                         Semester II
 Apr 5, 2012                           1
EEE2213                       2010/2011
THE DC OPERATING POINT
       A transistor must be properly biased with a dc
       voltage in order to operate as a linear amplifier.

       A dc operating point must be set so that signal
       variations at the input terminal are implified &
       accurately reproduced at the output terminal.

       Note that when we bias a transistor, the dc voltage
       and current values will be established.
       Thus, at the dc operating point, IC & VCE have
       specified values.
       Q-point: the dc operating point (quiescent point)
Apr 5, 2012                                                  2
DC Bias

       Bias establishes the dc operating point (Q-point)
       for proper linear operation of an amplifier.

       If an amplifier is not biased with correct dc
       voltages on the input and output, it can go into
       saturation or cutoff when an input signal is applied.




Apr 5, 2012                                                    3
FIGURE 5–1 Examples of linear and nonlinear operation of an inverting
amplifier (the triangle symbol).
Apr 5, 2012                                                         4
Figure 5-1 shows the effects of proper & improper
       dc biasing of an inverting amplifier.

       Part (a): Linear operation
       The output signal is an amplified replica of the
       input signal except that it is inverted, which means
       that it is 180° out of phase with the input.
       The output signal swings equally above & below
       the dc bias level of the output, V DC(out).
Apr 5, 2012                                                   5
Part (b & c): Nonlinear operation
       Improper biasing can cause distortion in the output
       signal.
       Part (b): shows the limiting of the positive portion
       of the output voltage as a result of a Q-point (dc
       operating point) being too close to cutoff.
       Part (c): shows the limiting of the negative portion
       of the output voltage as a result of a dc operating
       point being too close to saturation.
Apr 5, 2012                                                   6
Graphical Analysis
       The transistor in Figure is biased with VCC & VBB to obtain certain
       values of IB, IC, IE, and VCE.
       The collector characteristic curves for this particular transistor are
       shown in Figure.




Apr 5, 2012                                                                     7
Figure 5-3 Illustration of Q-point adjustment.
Apr 5, 2012                                                    8
Refer to Figure 5-3;
Assign 3 values to IB & observe what happens to IC & VCE.
First, VBB is adjusted to produce an IB of 200µA.
Since IC=βDCIB, the collector current is 20 mA, & VCE;
              VCE=VCC – ICRC = 10 V – (20 mA)(220Ω) = 10 V – 4.4 V = 5.6 V
                              (this Q-point is shown in (a) as Q1.)
Next, in (b);
VBB is increased to produce an IB of 300µA & an IC of 30 mA.
              VCE=VCC – ICRC = 10 V – (30 mA)(220Ω) = 10 V – 6.6 V = 3.4 V
                              (this Q-point is shown in (a) as Q2.)
Next, in (c);
VBB is increased to produce an IB of 400µA & an IC of 40 mA.
              VCE=VCC – ICRC = 10 V – (40 mA)(220Ω) = 10 V – 8.8 V = 1.2 V
Apr 5, 2012                                                                  9
DC Load Line
       The dc operation of a transistor circuit can be described graphically
       using a dc load line.
       DC Load Line: a straight line drawn on the characteristic curves from
       the saturation value where IC=IC(sat) on the y-axis to the cutoff value
       where VCE = VCC on the x-axis.




Apr 5, 2012                                                                      10
Load line is determined by the external circuit (VCC & RC), not
       determined by the transistor itself, which is described by the
       characteristic curve.




Apr 5, 2012                                                               11
Refer to Figure 5-3,
the equation for IC is;




This is the equation of a straight line with a slope of -1/RC, an x intercept of
VCE=VCC, & a y intercept of VCC/RC, which is IC(sat).
The point at which the load line intersects a characteristic curve represents the
Q-point for that particular value of IB.
Figure 5-4(b): shows the Q-point on the load line for each value of IB in Figure
5-3. 2012
Apr 5,                                                                         12
Linear Operation
       The region along the load line including all points between saturation &
       cutoff is generally known as the linear region of the transistor’s
       operation.
       As long as the transistor is operated in this region, the output voltage is
       ideally a linear reproduction of the input.




Apr 5, 2012                                                                          13
Figure shows an example of the linear operation of a transistor.
AC quantities are indicated by lowercase italic subscripts.
Assume a sinusoidal voltage, Vin, is superimposed on VBB, causing the base
current to vary sinusoidally 100 µA above and below its Q-point value of 300
µA.
This will causes the collector current to vary 10 mA above and below its Q-point
value of 30 mA.
From 2012 variation in collector current, the collector-to-emitter voltage varies
 Apr 5,
        the                                                                         14
Point A on the load line: corresponds to the positive peak of the sinusoidal input
voltage.
Point B on the load line: corresponds to the negative peak.
Point Q: corresponds to the zero value of the sine wave.
VCEQ, ICQ, & IBQ are dc Q-point values with no input sinusoidal voltage applied.
 Apr 5, 2012                                                                    15
Waveform Distortion
   Under certain input signal conditions, the location of the Q-point on the
   load line can cause one peak of the VCE waveform to be limited or clipped
   (Figure (a) & (b).




Apr 5, 2012                                                                    16
In each case, the input signal is too large for the Q-point location & is
   driving the transistor into cutoff or saturation during a portion of the input
   cycle.
   When both peaks are limited as in (c), the transistor is being driven into
   both saturation and cutoff by an excessively large input signal.


  When only the positive peak is
  limited, the transistor is being
  driven into cutoff but not
  saturation.


  When only the negative peak is
  limited, the transistor is being
  driven into saturation but not
  cutoff.


Apr 5, 2012                                                                         17
Example 5-1




Apr 5, 2012                 18
Lecture 9-2:

               TRANSISTOR BIAS
                   CIRCUITS
Code:                          Semester II
 Apr 5, 2012                           19
EEE2213                        2010/2011
VOLTAGE-DIVIDER BIAS
       A method of biasing a transistor for linear
       operation using a single-source resistive voltage
       divider.

       Earlier, a separate dc source, VBB, was used to bias
       the base-emitter junction because it could be
       varied independently of VCC, & it helped to
       illustrate transistor operation.

       More practical bias method: use VCC as the single
       bias source (refer next Figure).
Apr 5, 2012                                                   20
Apr 5, 2012   21
A dc bias voltage at the base of the transistor can be developed by a
resistive voltage divider that consists of R1 & R2.
VCC: the dc collector supply voltage
2 current paths are between point A & ground;
(2)through R2, and
(3)through the base-emitter junction of the transistor & RE
Generally, voltage-divider bias circuits are designed so that the
base current is much smaller than the current (I2) through R2.
For this case, the voltage-divider circuit is very straightforward to
analyze because the loading effect of the base current can be
ignored.
Stiff voltage divider: A voltage divider in which the base current
is small compared to the current in R2 (the base voltage is relatively
 Apr 5, 2012                                                        22
independent of different transistors & temperature effects).
To analyze a voltage-divider circuit in which IB is small
compared to R2, first calculate the voltage on the base;
R1 and R2 are selected to establish VB. If the divider is stiff,
IB is small compared to I2. Then,
                                                              +VCC
                R2                                          +15 V
          VB ≈           VCC
                R1 + R2 
                                                      R1      +VCCRC
                                                      27 kΩ       1.2 kΩ

      Determine the base voltage for the                           βDC = 200
                                                      R1          RC
      circuit.
                                                      IB
                                                      R2          RE
                                                      12 kΩ       680 Ω
                                                      I2
                R2 
          VB =           VCC
                R1 + R2                             R2          RE

                    12 kΩ     
             =                 ( +15 V ) = 4.62 V
                27 kΩ + 12 kΩ 
• Once we have the base voltage, we can find the
  voltages & currents in the circuit;



• and



• Then,



• From the VC & VE, we can determine VCE;

Apr 5, 2012                                        24
What is the emitter voltage, VE, and current, IE?


                                                    +VCC
                                                    +15 V
VE is one diode drop less than VB:
                                            R1          RC
                                            27 kΩ       1.2 kΩ

VE = 4.62 V – 0.7 V = 3.92 V                   4.62 V       βDC = 200

Applying Ohm’s law:                                         3.92 V
                                            R2          RE
                                            12 kΩ       680 Ω
       VE 3.92 V
IE =     =       = 5.76 mA
       RE 680 Ω
Example 5-2




Apr 5, 2012                 26
Ideally, a voltage-divider circuit is stiff; where transistor does
not appear as a significant load.
To determine if the divider is stiff or not, then need to examine
the dc input resistance looking in at the base.




Apr 5, 2012                                                          27
Loading Effects of Voltage-Divider Bias

               (1) DC Input Resistance at the
               Transistor Base

               (2) Stability of Voltage-
               Divider Bias


               (3) Voltage-Divider Biased
               PNP Transistor
 Apr 5, 2012                                    28
DC Input Resistance at the
                   Transistor Base
    The dc input resistance of the transistor is proportional to
   βDC, thus it will change for different transistors.
    When a transistor is operating in its linear region, the
   emitter current is βDC IB.
    When the emitter resistor is viewed from the base circuit,
   the resistor appears to be larger than its actual value by a
   factor of is βDC because of the current gain in the transistor.
   Thus,                                β DCVB
                         RIN (BASE ) =
                                         IE
    This is the effective load on the voltage divider illustrated
   in earlier Figure.
Apr 5, 2012                                                          29
 We can estimate the loading effect by comparing RIN(BASE) to
   the resistor R2 in the voltage divider.


    As long as RIN(BASE) is at least 10x larger than R2, the
   loading effect will be 10% or less & the voltage divider is
   stiff.


    If RIN(BASE) is less than 10x R2, it should be combined in
   parallel with R2.




Apr 5, 2012                                                       30
Example 5-3




Apr 5, 2012                 31
Stability of Voltage-Divider Bias
    Thevenin’s theorem is applied when
   analyze a voltage-divider biased
   transistor circuit for base current
   loading effects.


    1st, get an equivalent base-emitter
   circuit for this circuit using Thevenin’s
   theorem.




Apr 5, 2012                                    32
 Looking out from the base terminal, the bias circuit can be
redrawn as shown in this figure.
 Apply Thevenin’s theorem to the
circuit left of point A, with VCC replaced
by a short to ground & the transistor
disconnected from the circuit.
 The voltage at point A with respect to
ground is,




 and the resistance is,



  Apr 5, 2012                                                   33
 The Thevenin equivalent of the bias circuit, connected to the
transistor base, is as shown in the grey box in the figure.
 Applying Kirchhoff’s voltage law
around the equivalent base-emitter loop
gives,




 Substituting, using Ohm’s law, &
solving for VTH,


 Substituting IE / βDC for IB,


  Apr 5, 2012                                                     34
 Solving for IE,




 If RTH / βDC is small compared to RE, the
result is the same as for unloaded voltage
divider.
 Reason of why a voltage-divider bias is
widely used;
 Reasonably good bias stability is
achieved with a single supply voltage.
  Apr 5, 2012                                 35
The unloaded voltage divider approximation for VB
gives reasonable results. A more exact solution is to
Thevenize the input circuit.



                                           + VCC                    +VCC
                                           +15 V                    +15 V
 VTH = VB(no load)
                                                RC          R1          RC
 = 4.62 V                                       1.2 kΩ      27 kΩ       1.2 kΩ

 RTH = R1||R2 =       +V TH
                     4.62 V
                              +
                               R TH
                                   –   +
                                                βDC = 200                   βDC = 200
                                 IB   VBE –
  = 8.31 kΩ                   8.31 kΩ
                                            +               R2          RE
                                                RE
 The Thevenin                          IE
                                            –
                                                680 Ω       12 kΩ       680 Ω

 input circuit can
 be drawn
Now write KVL around the base emitter circuit and
solve for IE.


      VTH = I B RTH + VBE + I E RE                               + VCC
                                                                 +15 V
              VTH − VBE
      IE =
                 R
             RE + TH                                                  RC
                     β DC                                             1.2 kΩ
      Substituting and solving,             +V TH    R TH
                                                    +    –   +
             4.62 V − 0.7 V                4.62 V                     βDC = 200
      IE =                     = 5.43 mA               IB   VBE –
           680 Ω + 8.31 kΩ                          8.31 kΩ
                           200                                    +   RE
                                                             IE
and                                                               –
                                                                      680 Ω


VE = IERE = (5.43 mA)(0.68 kΩ)
= 3.69 V
Voltage-Divider Biased PNP
                   Transistor
 pnp transistor requires bias polarities opposite to the npn.
 This can be accomplished by using a negative collector supply
voltage: (a), or with a positive emitter supply voltage (b). 3rd
figure is same as (b), only that it is drawn upside down.




 Apr 5, 2012                                                     38
 Analysis procedure is the same as for an npn transistor circuit.


 For a stiff voltage divider (ignoring loading
effects),




 By Ohm’s law,




 Thus,



  Apr 5, 2012                                                        39
Determine IE for the pnp circuit. Assume a
            stiff voltage divider (no loading effect).



                                                        +VEE
                                                       +15 V
      R1 
VB =           VEE                           R2         RE
      R1 + R2                                12 kΩ      680 Ω
          27 kΩ                             10.4 V     11.1 V
   =                 ( +15.0 V ) = 10.4 V
      27 kΩ + 12 kΩ 
VE = VB + VBE = 10.4 V + 0.7 V = 11.1 V        R1         RC
                                               27 kΩ      1.2 kΩ
       VEE − VE 15.0 V − 11.1 V
IE =           =                = 5.74
         RE          680 Ω
                                  mA
Example 5-4 & 5-5




Apr 5, 2012                       41
EMITTER BIAS
       Provides excellent bias stability in spite of changes in β
       or temperature.

       Use both a positive & a negative supply voltage.
       In an npn circuit, the small
       base current causes the base
       voltage to be slightly below
       ground.
       The emitter voltage is one
       diode drop less than this.



Apr 5, 2012                                                         42
The combination of this small drop across RB & VBE forces
       the emitter to be at approximately -1 V.
       Thus, emitter current is,


Apr 5, 2012                                                        43
Applying the approximation that


       to calculate the collector voltage, thus

Apr 5, 2012                                       44
Apr 5, 2012   45
Example 5-6




Apr 5, 2012                 46
• Approximation that             & the neglect of βDC may not be
  accurate enough for design work or detailed analysis.
• Kirchhoff’s voltage law (KVL) can be applied to develop a
  more detailed formula for IE.
• In (a): KVL applied around the
  base-emitter circuit
• In (b): (a) is redrawn for
  analysis
• Thus,

                                    • Substitute                    &
                                      transposing VEE,
• Using Ohm’s law,


Apr 5, 2012                                                    47
• Thus,




• Voltages with respect to ground are indicated by a single
  subscript.
• Thus, the emitter voltage with respect to the ground is,



• The base voltage with respect to ground is,



• The collector with respect to the ground is,

Apr 5, 2012                                                   48
Example 5-7




Apr 5, 2012                 49
BASE BIAS
 This method of biasing is common in switching circuits.
 Analysis of this circuit for the linear region shows that it is
directly dependent on βDC.
 Starts with KVL around the base circuit,


 Substitutes IBRB for VRB,


Thus,


Apr 5, 2012                                                         50
 When KVL is applied around the collector circuit, we get,


 Thus,


 Substitute IC = βDCIB, we get,




Apr 5, 2012                                                   51
Base bias is used in switching circuits because of
its simplicity, but not widely used in linear
applications because the Q-point is β dependent.

Base current is derived from the collector
supply through a large base resistor.
                                                      +VCC
                                                      +VCC
                                                      +15 V

           What is IB?                                   RC
                                                         1.8 kΩ
                                              RB

                                             560 kΩ
       VCC − 0.7 V 15 V − 0.7 V
  IB =            =             = 25.5 µA
           RB        560 kΩ
Q-Point Stability of Base Bias
 Equation




   shows that IC is dependent on βDC. Thus, a variation in βDC causes
IC and, as a result, VCE to change, thus changing the Q-point of the
transistor. Therefore, the base bias circuit is extremely beta-
dependent & unpredictable.
 βDC varies with temperature & collector current.
 There is a large spread of βDC values from one transistor to
another of the same type due to manufacturing variations.
Apr 5, 2012                                                       53
 Therefore, base bias is rarely used in linear circuits.
Example 5-8




Apr 5, 2012                 54
EMITTER-FEEDBACK BIAS
 If an emitter resistor is added to the base-circuit, we get an
emitter-feedback bias.
 Help make base bias more predictable with
negative feedback, which negates any
attempted change in collector current with an
opposing change in base voltage.
 If the collector current tries to increase, the
emitter voltage increases, causing an increase in
base voltage due to VB = VE + VBE
 This increase in base voltage reduces the
voltage across RB, thus reducing the base
current & keeping the collector current from
increasing.
Apr 5, 2012                                                        55
The same scenario happens if the collector
current tries to decrease.
 This circuit is better for linear circuits than
base bias, but still dependent on βDC & is not
predictable as voltage-divider bias.
 To calculate IE, write KVL around the base
circuit.


Substitute IE/βDC for IB, can see that IE is still
dependent on βDC.




Apr 5, 2012                                           56
Example 5-9




Apr 5, 2012                 57
COLLECTOR-FEEDBACK BIAS
 The base resistor RB is connected to the collector rather than to
VCC.
 The collector voltage provides the bias for the base-
emitter junction.
 The negative feedback creates an “offsetting” effect
that tends to keep the Q-point stable.
 If IC tries to increase, it drops more voltage across RC,
and thus causing VC to decrease.

 When VC decreases, there is a decrease in voltage
across RB, which deecreases IB.

 The decrease in IB produces less IC which, in turn,
drops less voltage across RC & thus offsets the decrease
in VC.
Apr 5, 2012                                                      58
 By Ohm’s law,




 Assume that IC >> IB, thus the collector
voltage,


 Also,




 Thus,


Apr 5, 2012                                  59
 Thus,




 Since the emitter is ground, VCE = VC, then




Apr 5, 2012                                     60
Q-Point Stability Over
                 Temperature
 Equation




  shows that IC is dependent to some extent on βDC and VBE .

 The dependency can be minimized by making RC >> RB/βDC &
VCE >>VBE.

 The collector-feedback bias is essentially eliminates the βDC &
VBE dependency even if the stated conditions are met.

 βDC varies directly with temperature, & VBE varies inversely with
temperature. As the temperature goes up in a collector-feedback 61
 Apr 5, 2012 β
       DC
 The increase in βDC acts to increase IC. The decrease in
VBE acts to increase IB which, in turn also acts to increase
IC. As IC tries to increase, the voltage drop across RC also
tries to increase. This tends to reduce the collector voltage
& therefore the voltage across RB, thus reducing IB &
offsetting the attempted increase in IC & the attempted
decrease in VC.


 The result is that the collector-feedback circuit
maintains a relatively stable Q-point. The reverse action
occurs when the temperature decreases.
Apr 5, 2012 βDC                                           62
Compare IC for the case when β = 100 with the case
 when β = 300.


                                                                +VCC
When β = 100,                                                   + 15 V
      VCC − VBE         15 V − 0.7 V
IC =              =                      = 2.80 mA                 RC
          RB        1.8 kΩ + 330 kΩ                     RB
     RC +                            100                           1.8 kΩ
             β DC
                                                       330 kΩ
When β = 300,
        VCC − VBE         15 V − 0.7 V
IC =                =                      = 4.93 mA
            RB        1.8 kΩ + 330 kΩ
       RC +                            300
               β DC
Example 5-10




Apr 5, 2012                  64

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Transistor Bias Circuit Analysis

  • 1. Lecture : TRANSISTOR BIAS CIRCUITS Code: Semester II Apr 5, 2012 1 EEE2213 2010/2011
  • 2. THE DC OPERATING POINT A transistor must be properly biased with a dc voltage in order to operate as a linear amplifier. A dc operating point must be set so that signal variations at the input terminal are implified & accurately reproduced at the output terminal. Note that when we bias a transistor, the dc voltage and current values will be established. Thus, at the dc operating point, IC & VCE have specified values. Q-point: the dc operating point (quiescent point) Apr 5, 2012 2
  • 3. DC Bias Bias establishes the dc operating point (Q-point) for proper linear operation of an amplifier. If an amplifier is not biased with correct dc voltages on the input and output, it can go into saturation or cutoff when an input signal is applied. Apr 5, 2012 3
  • 4. FIGURE 5–1 Examples of linear and nonlinear operation of an inverting amplifier (the triangle symbol). Apr 5, 2012 4
  • 5. Figure 5-1 shows the effects of proper & improper dc biasing of an inverting amplifier. Part (a): Linear operation The output signal is an amplified replica of the input signal except that it is inverted, which means that it is 180° out of phase with the input. The output signal swings equally above & below the dc bias level of the output, V DC(out). Apr 5, 2012 5
  • 6. Part (b & c): Nonlinear operation Improper biasing can cause distortion in the output signal. Part (b): shows the limiting of the positive portion of the output voltage as a result of a Q-point (dc operating point) being too close to cutoff. Part (c): shows the limiting of the negative portion of the output voltage as a result of a dc operating point being too close to saturation. Apr 5, 2012 6
  • 7. Graphical Analysis The transistor in Figure is biased with VCC & VBB to obtain certain values of IB, IC, IE, and VCE. The collector characteristic curves for this particular transistor are shown in Figure. Apr 5, 2012 7
  • 8. Figure 5-3 Illustration of Q-point adjustment. Apr 5, 2012 8
  • 9. Refer to Figure 5-3; Assign 3 values to IB & observe what happens to IC & VCE. First, VBB is adjusted to produce an IB of 200µA. Since IC=βDCIB, the collector current is 20 mA, & VCE; VCE=VCC – ICRC = 10 V – (20 mA)(220Ω) = 10 V – 4.4 V = 5.6 V (this Q-point is shown in (a) as Q1.) Next, in (b); VBB is increased to produce an IB of 300µA & an IC of 30 mA. VCE=VCC – ICRC = 10 V – (30 mA)(220Ω) = 10 V – 6.6 V = 3.4 V (this Q-point is shown in (a) as Q2.) Next, in (c); VBB is increased to produce an IB of 400µA & an IC of 40 mA. VCE=VCC – ICRC = 10 V – (40 mA)(220Ω) = 10 V – 8.8 V = 1.2 V Apr 5, 2012 9
  • 10. DC Load Line The dc operation of a transistor circuit can be described graphically using a dc load line. DC Load Line: a straight line drawn on the characteristic curves from the saturation value where IC=IC(sat) on the y-axis to the cutoff value where VCE = VCC on the x-axis. Apr 5, 2012 10
  • 11. Load line is determined by the external circuit (VCC & RC), not determined by the transistor itself, which is described by the characteristic curve. Apr 5, 2012 11
  • 12. Refer to Figure 5-3, the equation for IC is; This is the equation of a straight line with a slope of -1/RC, an x intercept of VCE=VCC, & a y intercept of VCC/RC, which is IC(sat). The point at which the load line intersects a characteristic curve represents the Q-point for that particular value of IB. Figure 5-4(b): shows the Q-point on the load line for each value of IB in Figure 5-3. 2012 Apr 5, 12
  • 13. Linear Operation The region along the load line including all points between saturation & cutoff is generally known as the linear region of the transistor’s operation. As long as the transistor is operated in this region, the output voltage is ideally a linear reproduction of the input. Apr 5, 2012 13
  • 14. Figure shows an example of the linear operation of a transistor. AC quantities are indicated by lowercase italic subscripts. Assume a sinusoidal voltage, Vin, is superimposed on VBB, causing the base current to vary sinusoidally 100 µA above and below its Q-point value of 300 µA. This will causes the collector current to vary 10 mA above and below its Q-point value of 30 mA. From 2012 variation in collector current, the collector-to-emitter voltage varies Apr 5, the 14
  • 15. Point A on the load line: corresponds to the positive peak of the sinusoidal input voltage. Point B on the load line: corresponds to the negative peak. Point Q: corresponds to the zero value of the sine wave. VCEQ, ICQ, & IBQ are dc Q-point values with no input sinusoidal voltage applied. Apr 5, 2012 15
  • 16. Waveform Distortion Under certain input signal conditions, the location of the Q-point on the load line can cause one peak of the VCE waveform to be limited or clipped (Figure (a) & (b). Apr 5, 2012 16
  • 17. In each case, the input signal is too large for the Q-point location & is driving the transistor into cutoff or saturation during a portion of the input cycle. When both peaks are limited as in (c), the transistor is being driven into both saturation and cutoff by an excessively large input signal. When only the positive peak is limited, the transistor is being driven into cutoff but not saturation. When only the negative peak is limited, the transistor is being driven into saturation but not cutoff. Apr 5, 2012 17
  • 19. Lecture 9-2: TRANSISTOR BIAS CIRCUITS Code: Semester II Apr 5, 2012 19 EEE2213 2010/2011
  • 20. VOLTAGE-DIVIDER BIAS A method of biasing a transistor for linear operation using a single-source resistive voltage divider. Earlier, a separate dc source, VBB, was used to bias the base-emitter junction because it could be varied independently of VCC, & it helped to illustrate transistor operation. More practical bias method: use VCC as the single bias source (refer next Figure). Apr 5, 2012 20
  • 22. A dc bias voltage at the base of the transistor can be developed by a resistive voltage divider that consists of R1 & R2. VCC: the dc collector supply voltage 2 current paths are between point A & ground; (2)through R2, and (3)through the base-emitter junction of the transistor & RE Generally, voltage-divider bias circuits are designed so that the base current is much smaller than the current (I2) through R2. For this case, the voltage-divider circuit is very straightforward to analyze because the loading effect of the base current can be ignored. Stiff voltage divider: A voltage divider in which the base current is small compared to the current in R2 (the base voltage is relatively Apr 5, 2012 22 independent of different transistors & temperature effects).
  • 23. To analyze a voltage-divider circuit in which IB is small compared to R2, first calculate the voltage on the base; R1 and R2 are selected to establish VB. If the divider is stiff, IB is small compared to I2. Then, +VCC  R2  +15 V VB ≈   VCC  R1 + R2  R1 +VCCRC 27 kΩ 1.2 kΩ Determine the base voltage for the βDC = 200 R1 RC circuit. IB R2 RE 12 kΩ 680 Ω I2  R2  VB =   VCC  R1 + R2  R2 RE  12 kΩ  =  ( +15 V ) = 4.62 V  27 kΩ + 12 kΩ 
  • 24. • Once we have the base voltage, we can find the voltages & currents in the circuit; • and • Then, • From the VC & VE, we can determine VCE; Apr 5, 2012 24
  • 25. What is the emitter voltage, VE, and current, IE? +VCC +15 V VE is one diode drop less than VB: R1 RC 27 kΩ 1.2 kΩ VE = 4.62 V – 0.7 V = 3.92 V 4.62 V βDC = 200 Applying Ohm’s law: 3.92 V R2 RE 12 kΩ 680 Ω VE 3.92 V IE = = = 5.76 mA RE 680 Ω
  • 27. Ideally, a voltage-divider circuit is stiff; where transistor does not appear as a significant load. To determine if the divider is stiff or not, then need to examine the dc input resistance looking in at the base. Apr 5, 2012 27
  • 28. Loading Effects of Voltage-Divider Bias (1) DC Input Resistance at the Transistor Base (2) Stability of Voltage- Divider Bias (3) Voltage-Divider Biased PNP Transistor Apr 5, 2012 28
  • 29. DC Input Resistance at the Transistor Base  The dc input resistance of the transistor is proportional to βDC, thus it will change for different transistors.  When a transistor is operating in its linear region, the emitter current is βDC IB.  When the emitter resistor is viewed from the base circuit, the resistor appears to be larger than its actual value by a factor of is βDC because of the current gain in the transistor. Thus, β DCVB RIN (BASE ) = IE  This is the effective load on the voltage divider illustrated in earlier Figure. Apr 5, 2012 29
  • 30.  We can estimate the loading effect by comparing RIN(BASE) to the resistor R2 in the voltage divider.  As long as RIN(BASE) is at least 10x larger than R2, the loading effect will be 10% or less & the voltage divider is stiff.  If RIN(BASE) is less than 10x R2, it should be combined in parallel with R2. Apr 5, 2012 30
  • 32. Stability of Voltage-Divider Bias  Thevenin’s theorem is applied when analyze a voltage-divider biased transistor circuit for base current loading effects.  1st, get an equivalent base-emitter circuit for this circuit using Thevenin’s theorem. Apr 5, 2012 32
  • 33.  Looking out from the base terminal, the bias circuit can be redrawn as shown in this figure.  Apply Thevenin’s theorem to the circuit left of point A, with VCC replaced by a short to ground & the transistor disconnected from the circuit.  The voltage at point A with respect to ground is,  and the resistance is, Apr 5, 2012 33
  • 34.  The Thevenin equivalent of the bias circuit, connected to the transistor base, is as shown in the grey box in the figure.  Applying Kirchhoff’s voltage law around the equivalent base-emitter loop gives,  Substituting, using Ohm’s law, & solving for VTH,  Substituting IE / βDC for IB, Apr 5, 2012 34
  • 35.  Solving for IE,  If RTH / βDC is small compared to RE, the result is the same as for unloaded voltage divider.  Reason of why a voltage-divider bias is widely used;  Reasonably good bias stability is achieved with a single supply voltage. Apr 5, 2012 35
  • 36. The unloaded voltage divider approximation for VB gives reasonable results. A more exact solution is to Thevenize the input circuit. + VCC +VCC +15 V +15 V VTH = VB(no load) RC R1 RC = 4.62 V 1.2 kΩ 27 kΩ 1.2 kΩ RTH = R1||R2 = +V TH 4.62 V + R TH – + βDC = 200 βDC = 200 IB VBE – = 8.31 kΩ 8.31 kΩ + R2 RE RE The Thevenin IE – 680 Ω 12 kΩ 680 Ω input circuit can be drawn
  • 37. Now write KVL around the base emitter circuit and solve for IE. VTH = I B RTH + VBE + I E RE + VCC +15 V VTH − VBE IE = R RE + TH RC β DC 1.2 kΩ Substituting and solving, +V TH R TH + – + 4.62 V − 0.7 V 4.62 V βDC = 200 IE = = 5.43 mA IB VBE – 680 Ω + 8.31 kΩ 8.31 kΩ 200 + RE IE and – 680 Ω VE = IERE = (5.43 mA)(0.68 kΩ) = 3.69 V
  • 38. Voltage-Divider Biased PNP Transistor  pnp transistor requires bias polarities opposite to the npn.  This can be accomplished by using a negative collector supply voltage: (a), or with a positive emitter supply voltage (b). 3rd figure is same as (b), only that it is drawn upside down. Apr 5, 2012 38
  • 39.  Analysis procedure is the same as for an npn transistor circuit.  For a stiff voltage divider (ignoring loading effects),  By Ohm’s law,  Thus, Apr 5, 2012 39
  • 40. Determine IE for the pnp circuit. Assume a stiff voltage divider (no loading effect). +VEE +15 V  R1  VB =   VEE R2 RE  R1 + R2  12 kΩ 680 Ω  27 kΩ  10.4 V 11.1 V =  ( +15.0 V ) = 10.4 V  27 kΩ + 12 kΩ  VE = VB + VBE = 10.4 V + 0.7 V = 11.1 V R1 RC 27 kΩ 1.2 kΩ VEE − VE 15.0 V − 11.1 V IE = = = 5.74 RE 680 Ω mA
  • 41. Example 5-4 & 5-5 Apr 5, 2012 41
  • 42. EMITTER BIAS Provides excellent bias stability in spite of changes in β or temperature. Use both a positive & a negative supply voltage. In an npn circuit, the small base current causes the base voltage to be slightly below ground. The emitter voltage is one diode drop less than this. Apr 5, 2012 42
  • 43. The combination of this small drop across RB & VBE forces the emitter to be at approximately -1 V. Thus, emitter current is, Apr 5, 2012 43
  • 44. Applying the approximation that to calculate the collector voltage, thus Apr 5, 2012 44
  • 47. • Approximation that & the neglect of βDC may not be accurate enough for design work or detailed analysis. • Kirchhoff’s voltage law (KVL) can be applied to develop a more detailed formula for IE. • In (a): KVL applied around the base-emitter circuit • In (b): (a) is redrawn for analysis • Thus, • Substitute & transposing VEE, • Using Ohm’s law, Apr 5, 2012 47
  • 48. • Thus, • Voltages with respect to ground are indicated by a single subscript. • Thus, the emitter voltage with respect to the ground is, • The base voltage with respect to ground is, • The collector with respect to the ground is, Apr 5, 2012 48
  • 50. BASE BIAS  This method of biasing is common in switching circuits.  Analysis of this circuit for the linear region shows that it is directly dependent on βDC.  Starts with KVL around the base circuit,  Substitutes IBRB for VRB, Thus, Apr 5, 2012 50
  • 51.  When KVL is applied around the collector circuit, we get,  Thus,  Substitute IC = βDCIB, we get, Apr 5, 2012 51
  • 52. Base bias is used in switching circuits because of its simplicity, but not widely used in linear applications because the Q-point is β dependent. Base current is derived from the collector supply through a large base resistor. +VCC +VCC +15 V What is IB? RC 1.8 kΩ RB 560 kΩ VCC − 0.7 V 15 V − 0.7 V IB = = = 25.5 µA RB 560 kΩ
  • 53. Q-Point Stability of Base Bias  Equation shows that IC is dependent on βDC. Thus, a variation in βDC causes IC and, as a result, VCE to change, thus changing the Q-point of the transistor. Therefore, the base bias circuit is extremely beta- dependent & unpredictable.  βDC varies with temperature & collector current.  There is a large spread of βDC values from one transistor to another of the same type due to manufacturing variations. Apr 5, 2012 53  Therefore, base bias is rarely used in linear circuits.
  • 55. EMITTER-FEEDBACK BIAS  If an emitter resistor is added to the base-circuit, we get an emitter-feedback bias.  Help make base bias more predictable with negative feedback, which negates any attempted change in collector current with an opposing change in base voltage.  If the collector current tries to increase, the emitter voltage increases, causing an increase in base voltage due to VB = VE + VBE  This increase in base voltage reduces the voltage across RB, thus reducing the base current & keeping the collector current from increasing. Apr 5, 2012 55
  • 56. The same scenario happens if the collector current tries to decrease.  This circuit is better for linear circuits than base bias, but still dependent on βDC & is not predictable as voltage-divider bias.  To calculate IE, write KVL around the base circuit. Substitute IE/βDC for IB, can see that IE is still dependent on βDC. Apr 5, 2012 56
  • 58. COLLECTOR-FEEDBACK BIAS  The base resistor RB is connected to the collector rather than to VCC.  The collector voltage provides the bias for the base- emitter junction.  The negative feedback creates an “offsetting” effect that tends to keep the Q-point stable.  If IC tries to increase, it drops more voltage across RC, and thus causing VC to decrease.  When VC decreases, there is a decrease in voltage across RB, which deecreases IB.  The decrease in IB produces less IC which, in turn, drops less voltage across RC & thus offsets the decrease in VC. Apr 5, 2012 58
  • 59.  By Ohm’s law,  Assume that IC >> IB, thus the collector voltage,  Also,  Thus, Apr 5, 2012 59
  • 60.  Thus,  Since the emitter is ground, VCE = VC, then Apr 5, 2012 60
  • 61. Q-Point Stability Over Temperature  Equation shows that IC is dependent to some extent on βDC and VBE .  The dependency can be minimized by making RC >> RB/βDC & VCE >>VBE.  The collector-feedback bias is essentially eliminates the βDC & VBE dependency even if the stated conditions are met.  βDC varies directly with temperature, & VBE varies inversely with temperature. As the temperature goes up in a collector-feedback 61 Apr 5, 2012 β DC
  • 62.  The increase in βDC acts to increase IC. The decrease in VBE acts to increase IB which, in turn also acts to increase IC. As IC tries to increase, the voltage drop across RC also tries to increase. This tends to reduce the collector voltage & therefore the voltage across RB, thus reducing IB & offsetting the attempted increase in IC & the attempted decrease in VC.  The result is that the collector-feedback circuit maintains a relatively stable Q-point. The reverse action occurs when the temperature decreases. Apr 5, 2012 βDC 62
  • 63. Compare IC for the case when β = 100 with the case when β = 300. +VCC When β = 100, + 15 V VCC − VBE 15 V − 0.7 V IC = = = 2.80 mA RC RB 1.8 kΩ + 330 kΩ RB RC + 100 1.8 kΩ β DC 330 kΩ When β = 300, VCC − VBE 15 V − 0.7 V IC = = = 4.93 mA RB 1.8 kΩ + 330 kΩ RC + 300 β DC

Notas del editor

  1. Chapter 2 Apr 5, 2012 'ASYIQ
  2. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  3. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  4. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  5. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  6. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  7. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  8. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  9. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  10. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  11. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  12. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  13. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  14. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  15. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  16. Chapter 2 Apr 5, 2012 'ASYIQ
  17. Apr 5, 2012 'ASYIQ
  18. Stiff: firm Apr 5, 2012 'ASYIQ
  19. Apr 5, 2012 'ASYIQ
  20. Apr 5, 2012 'ASYIQ
  21. Apr 5, 2012 'ASYIQ
  22. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  23. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  24. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  25. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  26. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  27. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  28. Apr 5, 2012 'ASYIQ
  29. Apr 5, 2012 'ASYIQ
  30. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  31. Fig 4-2a & b Apr 5, 2012 'ASYIQ
  32. Apr 5, 2012 'ASYIQ
  33. Figure 5-18 Apr 5, 2012 'ASYIQ
  34. Figure 5-18 Apr 5, 2012 'ASYIQ
  35. Figure 5-18 Apr 5, 2012 'ASYIQ
  36. Figure 5-18 Apr 5, 2012 'ASYIQ
  37. Figure 5-18 Apr 5, 2012 'ASYIQ
  38. Figure 5-18 Apr 5, 2012 'ASYIQ
  39. Figure 5-18 Apr 5, 2012 'ASYIQ
  40. Apr 5, 2012 'ASYIQ
  41. Figure 5-18 Apr 5, 2012 'ASYIQ
  42. Figure 5-18 Negates: cancels out Apr 5, 2012 'ASYIQ
  43. Figure 5-18 Negates: cancels out Apr 5, 2012 'ASYIQ
  44. Figure 5-18 Negates: cancels out Apr 5, 2012 'ASYIQ
  45. Figure 5-18 Negates: cancels out Apr 5, 2012 'ASYIQ
  46. Figure 5-18 Negates: cancels out Apr 5, 2012 'ASYIQ
  47. Figure 5-18 Apr 5, 2012 'ASYIQ
  48. Figure 5-18 Apr 5, 2012 'ASYIQ
  49. Apr 5, 2012 'ASYIQ