This document provides an overview of logic gates and digital logic circuits. It defines common logic gates like AND, OR, NOT, NAND and NOR. It describes transistor-transistor logic (TTL) and complementary metal-oxide-semiconductor (CMOS) logic families and their characteristics. Examples of logic circuits using TTL and CMOS gates are also presented.

1. Logic Gates Digital Logic and Software Principles © University of Wales Newport 2009 This work is licensed under a Creative Commons Attribution 2.0 License .

7. We can have more than two inputs in which case the only time we would have a 0 out is when all the inputs are false. American (MIL-STD-806) British (IEC 617:12) Logic Gates A B Y 0 0 0 1 1 0 1 1 A B Y 0 0 0 0 1 1 1 0 1 1 1 1 A A B B Y Y  1

9. We can only have one input and the output is always the opposite sign. American (MIL-STD-806) British (IEC 617:12) Logic Gates A Y 0 1 1 0 A A Y Y 1

11. Exclusive OR EXOR gate where the  sign represents logical EXOR. Note that the normal OR includes the case where we have both inputs true. The EXOR does not include this case. For more than two inputs the gate is defined as: The output is TRUE if we have an odd number of inputs TRUE Logic Gates A B Y 0 0 0 1 1 0 1 1 A B Y 0 0 0 0 1 1 1 0 1 1 1 0

13. Not AND NAND gate where the dot and bar represents logical NAND. We can have more than two inputs in which case the only time we would have a 0 out is when all the inputs are true. American (MIL-STD-806) British (IEC 617:12) Logic Gates A B Y 0 0 0 1 1 0 1 1 1 1 1 0 A B Y & A B Y

14. Not OR NOR gate where the + sign and bar represents logical NAND. We can have more than two inputs in which case the only time we would have a 1 out is when all the inputs are false. American (MIL-STD-806) British (IEC 617:12) Logic Gates A B Y 0 0 0 1 1 0 1 1 1 0 0 0 A A B B Y Y  1

16. NOT using NANDs only The Truth Table is for a NAND gate If we tie the inputs of a NAND together then we limit the possible input combinations to two, 1 1 and 0 0. These are shown on the table now if the input is 0 the output is 1 and vice versa – a NOT gate Logic Gates A B Y 0 0 1 0 1 1 1 0 1 1 1 0 A Y

18. OR using NANDs only This is our desired OR gate Logic Gates 0 0 0 0 1 1 1 0 1 1 1 1

19. OR using NANDs only If we now add NOT A and NOT B into our table Logic Gates 0 0 0 1 1 0 1 1 1 0 1 0 1 0 1 1 1 1 0 0

20. OR using NANDs only If these are now ANDed together Logic Gates 0 0 0 1 1 1 0 1 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 0

21. OR using NANDs only Finally if we invert our result we see that the 3 rd and 7 th column are identical. This means that if we invert the inputs then NAND then we will end up with the OR function. Logic Gates 0 0 0 1 1 1 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1

22. OR using NANDs only Let us examine the way in which logic gates can be used to realise logic circuits: Logic Gates A B Y

37. Convert the circuit to NAND only. Note. We require: 8 x 2-input NAND 2 x 7400 1 x 3-input NAND 1 x 7410 again 3 chips . Logic Gates OR AND AND NOT 1 2 3 4 5 6 7 8 9

43. * dependant on frequency Logic Gates Technology Silicon gate CMOS Metal gate CMOS Std TTL Low-power Schottky TTL Schottky TTL Advanced Low – power Schottky TTL Advanced Schottky TTL Device series SN74HC 4000 SN74 SN74LS SN74AS SN74ALS SN74AS Power diss per gate (mW) Static At 100kHz 0.0000025 0.17 0.001 0.1 10 10 2 2 19 19 1 1 8.5 8.5 Progation delay time (nS) 8 105 10 10 3 4 1.5 Maximun clock (MHz) 40 12 35 40 125 70 200 Maximum output drive (mA) 4 1.6 16 8 20 8 20 Fan out LS loads Same series 10 * 4 * 40 10 20 20 50 10 20 80 50 40 Maximum input current(mA)  0.0001 -0.0001 -1.6 -0.4 -2.0 -0.1 -0.5

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