SlideShare una empresa de Scribd logo
1 de 6
Descargar para leer sin conexión
-
                                                        250       -




                                       ESSCIRC'85

             RTB: A Full-Duplex ECL Transceiver For Wideband Digital
                                             Systems.
                     Piero Belforte Vanni Poletto Mario Sartori
                                       -                      -




                 CSELT (Centro Studi e Laboratori Telecomunicazioni)
            1014B Torino (Italy), via G. Reiss Romoli 274, Tel. 39-11-21691


                                           Summary
    This paper deals with the design of a low cost ECL bipolar compatible I.C
performing the function of four balanced full-duplex transceivers particularly
suitable for interconnections      long          up to several tens of meters in            digital
systems.
    One of the most    interesting applications of this circuit is in the field of
wideband digital switching (up to 100 Mbit/sec) where the amount of two-way
internal connections can be very high, [l] More precisely when bidirectional
video communications are concerned (as in the case of the digital switching of
video telephony signals) the use of this component virtually halves the wiring
cost. Other applications include narrow band (up to 2 Mbit/sec) digital switching
systems where it is possible to achieve great saving in cabling cost or to allow
the designers to implement interesting diagnosis and signalling schemes inside
the exchange.[2] Obviously his application range is not bounded to these fields
but covers all the situations where two-way communication implying the use of
standard receiver/transmitter pairs is needed.
    The functional behaviour of RTB is shown in fig. 1:
    Ct is   an   ECL driver with   a       low   output inpedance, Ip   is    a common      mode
current source, Ro is the line characteristic resistance,                    A1(A2)   are   linear
amplifiers, Cr is a differential to single ended ECL translator.
    (.) Patents pending
-
                                                     251   -




       When two transceivers    sending data through the same line, the signal at
                               are

both end of the line is a superposition of the one transmitted from the local
terminal and the one received from the remote terminal. The line signal swing is
a bit larger than the standard ECL but down-shifted about .8 V. The circuit

subtracts from the line signal the contribution due to trasmitter, taking into
account the 6 dB attenuation caused by the line impedance matching. In ideal
conditions (lossless cable and negligible output impedance of the driver), it is
easy to show that, if the gain of Al is a half of the gain of A2, a complete
cancellation of the transmitted signal occurs. In such a way the output
translator Cr has the function of restoring the ECL level compatibility.
       As the circuit   recovers     the   incoming signal     wave, it is easy to    gain
information about    an   abnormal state of the link       (cut or shorted).   This feature
also supplies a very simple method for testing the circuit; in fact, when the line
is open, the signal decoded at the receiving side of the tranceiver is equal to the
transmitted one, while when it is shorted the complement of the transmitted
signal can be found at the output. Therefore, connecting both open and shorted
the four tranceivers' line outputs, allows to check the correct behaviour of the
device.

            chip four different functions are present, each one working in a fully
       In the
independent mode, so attention must be paid to avoid crosstalk among them.
For this reason a careful design was made of the common bias circuit to obtain
an efficient decoupling.

       The main goal of thedesign was to achieve the best trade-off between speed
and power dissipation. For this reason a new low dissipation switched-load line
driver (*) suitable for ECL circuitry was developed, [fig. 2] The power
consumption of the drivers is externally programmable according to bit-rate
requirements and length of the cable interconnection; this is obtained through
an internally built voltage reference and an external programming resistor. In

the chip's architecture the bias circuit is shared by the four transceivers and a
-
                                                       252    -




power saving is gained in it        owing to the availability of complementary current
mirrors and amplifiers. (*)

    The I.C.      designed following both traditional and new methodological
                was

approaches. In particular the optimization of the circuit from the point of view
of speed was carried out using advanced characterization and simulation
techniques. The choice of the sizes and geometries of transistors making up the
main circuit blocks        (current switches, buffers, etc.) was           the consequence of
their time-domain         reflectometer (TDR) characterization.            The TDR responses
have been obtained from            a   set of standard       kit-parts   available   on   SGS LLV
process. From these TDR responses very accurate macromodels of circuit blocks
are obtained using fitting programs. The very close integration between

computerized measurements and simulation tools allows the designer to obtain
very quickly and easily the optimized parameters of macromodels. [fig. 3] These
macromodels and their related parameters are then used to simulate the
internal behaviour, mainly concerning critical paths, in the integrated circuit. A
similar   technique      was   also utilized for pin level electrical characterization of
the whole circuit.
    The real world operation where two similar tranceivers are interconnected
through an external lossy cable was then analyzed. In this case the actual cable
is directly modeled by its time-domain scattering parameters. Suitable
simulation programs [3] utilize both I.C. and cable models for the analysis of
situations which are not covered by standard simulation aids. The results of
these evaluations for various bit-rates and cable  lengths are shown in the paper
[fig. 4]. Chip's photograph and sizes are shown in Fig. 5.
     Finally the main features of the implemented chip are given including
electrical performances [fig. 6] and actual measurements in real operating
conditions,   [fig. 7]
    The RTB is      now    inserted    as   standard   component     among telecom I.Cs       by
S.G.S ATES.
-
                                              253   -




Acknowledgments
    The authors wish to thank    particularly Dr. Siligoni and Dr. Garue   of S.G.S
ATES for their useful advices during the developement of the circuit.

Bibliography
    [l]   Enzo Garetti Piero Belforte Luciano Gabrieili
   "New switching  techniques for wideband and ISDN environments"
   International Switching Symposium'84 (ISS '84) Florence

    [2]   Piero Belforte Enzo Garetti
   "A new generation of LSI   switching networks"
    FORUM 'B3 Geneva.
               -




    [3]   Piero Belforte Bruno Bostica Giancarlo Guaschino
   'Time domain simulation of lossy interconnections using
   wave digital networks"
   International Symposium on Circuits and Systems (ISCAS '82)
   Roma, May 10-12, 1982
-
                                                                             254   -




                                                                                   snfeUb
                                                                                   b

                                                                                            '-|r.o)¿                    -^O-i
                                                                                                                                           Po




                                                                                                                 §1' et.i'a
                                                                                   Fig. 2       -   Switched current load
                                                                                                                                       f
                                                                                                                            Line.driver.




                                                                                       -TWHE J/77Ef?       (X)    vs.   DATA RATE   (L=4m-24m   FULL   DUPLEX)
í GAMMA (my)                                                          Mp«)



                                                400pl




                                                        I
                                                            fSrtflV
 r(oo).r(R^).-7IOmS       equivalent              T-2BB NO/VIV
                          circuit
                          response                                                                                                                               p(Mbiu<.;

Fig.3   -
            Fitting   of the emitter follower T.D.R. response                      Fig.     4       -
                                                                                                        Time jitter computer evaluation for different
            using a   macromodel.                                                                       interconnection lengths (100 balanced ribbon
                                                                                                        cable).
-
                                                        255   -




-
    Main electrical characteristics.
-
    Voltage supply     5V            +_ lou
-
    Power consumption 660 mW
-
    Input and output levels       ECL 10K canpatibile
-
    Typical Input-output delay
    time (transmitter + receiver) 7 ns




                                                                  IÎ&L _7   .
                                                                                Receivers ' output Eye patterns in real operating ccnditlans.
                                                                                (TVo functions connected through 8 meter ribbon cable)
                                                                                Upper : 50 M bit/sec.
                                                                                Lower : 100 Kbit/sec uncorrelated.




    Fig. 5    -
                  Chip's photograph (device             area       3.2      mm2 pad       area    =   25%)

Más contenido relacionado

Más de Piero Belforte

Simulation-modeling matrix
Simulation-modeling matrixSimulation-modeling matrix
Simulation-modeling matrixPiero Belforte
 
Frequency domain behavior of S-parameters piecewise-linear fitting in a digit...
Frequency domain behavior of S-parameters piecewise-linear fitting in a digit...Frequency domain behavior of S-parameters piecewise-linear fitting in a digit...
Frequency domain behavior of S-parameters piecewise-linear fitting in a digit...Piero Belforte
 
3 experimental wideband_characterization_of_a parallel-plate_capacitor
3 experimental wideband_characterization_of_a parallel-plate_capacitor3 experimental wideband_characterization_of_a parallel-plate_capacitor
3 experimental wideband_characterization_of_a parallel-plate_capacitorPiero Belforte
 
Automated Piecewise-Linear Fitting of S-Parameters step-response (PWLFIT) for...
Automated Piecewise-Linear Fitting of S-Parameters step-response (PWLFIT) for...Automated Piecewise-Linear Fitting of S-Parameters step-response (PWLFIT) for...
Automated Piecewise-Linear Fitting of S-Parameters step-response (PWLFIT) for...Piero Belforte
 
Cseltmuseum post records from September 2018 to January2019
Cseltmuseum post records from September 2018 to January2019Cseltmuseum post records from September 2018 to January2019
Cseltmuseum post records from September 2018 to January2019Piero Belforte
 
Cseltmuseum post records August2018
Cseltmuseum post records August2018Cseltmuseum post records August2018
Cseltmuseum post records August2018Piero Belforte
 
Cseltmuseum post records July 2018
Cseltmuseum post records July 2018Cseltmuseum post records July 2018
Cseltmuseum post records July 2018Piero Belforte
 
Multigigabit modeling of hi safe+ flying probe fp011
Multigigabit modeling of hi safe+ flying probe fp011Multigigabit modeling of hi safe+ flying probe fp011
Multigigabit modeling of hi safe+ flying probe fp011Piero Belforte
 
Cseltmuseum post records June 2018
Cseltmuseum post records June 2018Cseltmuseum post records June 2018
Cseltmuseum post records June 2018Piero Belforte
 
CSELTMUSEUM POST RECORDS MAY 2018
CSELTMUSEUM POST RECORDS MAY 2018CSELTMUSEUM POST RECORDS MAY 2018
CSELTMUSEUM POST RECORDS MAY 2018Piero Belforte
 
CSELTMUSEUM POST RECORDS APRIL 2018
CSELTMUSEUM POST RECORDS APRIL 2018CSELTMUSEUM POST RECORDS APRIL 2018
CSELTMUSEUM POST RECORDS APRIL 2018Piero Belforte
 
CSELTMUSEUM post records March_2018
CSELTMUSEUM  post records March_2018CSELTMUSEUM  post records March_2018
CSELTMUSEUM post records March_2018Piero Belforte
 
CSELTMUSEUM POST RECORDS FEBRUARY 2018
CSELTMUSEUM POST RECORDS FEBRUARY  2018CSELTMUSEUM POST RECORDS FEBRUARY  2018
CSELTMUSEUM POST RECORDS FEBRUARY 2018Piero Belforte
 
CSELTMUSEUM POST RECORDS JANUARY 2018
CSELTMUSEUM POST RECORDS JANUARY 2018CSELTMUSEUM POST RECORDS JANUARY 2018
CSELTMUSEUM POST RECORDS JANUARY 2018Piero Belforte
 
CSELTMUSEUM expanded post records, December 2017
CSELTMUSEUM expanded post records, December 2017CSELTMUSEUM expanded post records, December 2017
CSELTMUSEUM expanded post records, December 2017Piero Belforte
 
HDT (High Design Technology) related content on Cseltmuseum Dec. 13 2017
HDT (High Design Technology) related content on Cseltmuseum  Dec. 13 2017HDT (High Design Technology) related content on Cseltmuseum  Dec. 13 2017
HDT (High Design Technology) related content on Cseltmuseum Dec. 13 2017Piero Belforte
 
HiSAFE related content on Cseltmuseum Dec. 13 2017
HiSAFE related content on Cseltmuseum Dec. 13 2017 HiSAFE related content on Cseltmuseum Dec. 13 2017
HiSAFE related content on Cseltmuseum Dec. 13 2017 Piero Belforte
 
CSELTMUSEUM post record August to December 2017
 CSELTMUSEUM post record August to December 2017 CSELTMUSEUM post record August to December 2017
CSELTMUSEUM post record August to December 2017Piero Belforte
 
Piero Belforte related presentations on slideplayer.com july 12 2017
Piero Belforte related presentations on slideplayer.com july 12 2017Piero Belforte related presentations on slideplayer.com july 12 2017
Piero Belforte related presentations on slideplayer.com july 12 2017Piero Belforte
 
Collection of Cselt related presentations on slideplayer.com by_Piero_Belfort...
Collection of Cselt related presentations on slideplayer.com by_Piero_Belfort...Collection of Cselt related presentations on slideplayer.com by_Piero_Belfort...
Collection of Cselt related presentations on slideplayer.com by_Piero_Belfort...Piero Belforte
 

Más de Piero Belforte (20)

Simulation-modeling matrix
Simulation-modeling matrixSimulation-modeling matrix
Simulation-modeling matrix
 
Frequency domain behavior of S-parameters piecewise-linear fitting in a digit...
Frequency domain behavior of S-parameters piecewise-linear fitting in a digit...Frequency domain behavior of S-parameters piecewise-linear fitting in a digit...
Frequency domain behavior of S-parameters piecewise-linear fitting in a digit...
 
3 experimental wideband_characterization_of_a parallel-plate_capacitor
3 experimental wideband_characterization_of_a parallel-plate_capacitor3 experimental wideband_characterization_of_a parallel-plate_capacitor
3 experimental wideband_characterization_of_a parallel-plate_capacitor
 
Automated Piecewise-Linear Fitting of S-Parameters step-response (PWLFIT) for...
Automated Piecewise-Linear Fitting of S-Parameters step-response (PWLFIT) for...Automated Piecewise-Linear Fitting of S-Parameters step-response (PWLFIT) for...
Automated Piecewise-Linear Fitting of S-Parameters step-response (PWLFIT) for...
 
Cseltmuseum post records from September 2018 to January2019
Cseltmuseum post records from September 2018 to January2019Cseltmuseum post records from September 2018 to January2019
Cseltmuseum post records from September 2018 to January2019
 
Cseltmuseum post records August2018
Cseltmuseum post records August2018Cseltmuseum post records August2018
Cseltmuseum post records August2018
 
Cseltmuseum post records July 2018
Cseltmuseum post records July 2018Cseltmuseum post records July 2018
Cseltmuseum post records July 2018
 
Multigigabit modeling of hi safe+ flying probe fp011
Multigigabit modeling of hi safe+ flying probe fp011Multigigabit modeling of hi safe+ flying probe fp011
Multigigabit modeling of hi safe+ flying probe fp011
 
Cseltmuseum post records June 2018
Cseltmuseum post records June 2018Cseltmuseum post records June 2018
Cseltmuseum post records June 2018
 
CSELTMUSEUM POST RECORDS MAY 2018
CSELTMUSEUM POST RECORDS MAY 2018CSELTMUSEUM POST RECORDS MAY 2018
CSELTMUSEUM POST RECORDS MAY 2018
 
CSELTMUSEUM POST RECORDS APRIL 2018
CSELTMUSEUM POST RECORDS APRIL 2018CSELTMUSEUM POST RECORDS APRIL 2018
CSELTMUSEUM POST RECORDS APRIL 2018
 
CSELTMUSEUM post records March_2018
CSELTMUSEUM  post records March_2018CSELTMUSEUM  post records March_2018
CSELTMUSEUM post records March_2018
 
CSELTMUSEUM POST RECORDS FEBRUARY 2018
CSELTMUSEUM POST RECORDS FEBRUARY  2018CSELTMUSEUM POST RECORDS FEBRUARY  2018
CSELTMUSEUM POST RECORDS FEBRUARY 2018
 
CSELTMUSEUM POST RECORDS JANUARY 2018
CSELTMUSEUM POST RECORDS JANUARY 2018CSELTMUSEUM POST RECORDS JANUARY 2018
CSELTMUSEUM POST RECORDS JANUARY 2018
 
CSELTMUSEUM expanded post records, December 2017
CSELTMUSEUM expanded post records, December 2017CSELTMUSEUM expanded post records, December 2017
CSELTMUSEUM expanded post records, December 2017
 
HDT (High Design Technology) related content on Cseltmuseum Dec. 13 2017
HDT (High Design Technology) related content on Cseltmuseum  Dec. 13 2017HDT (High Design Technology) related content on Cseltmuseum  Dec. 13 2017
HDT (High Design Technology) related content on Cseltmuseum Dec. 13 2017
 
HiSAFE related content on Cseltmuseum Dec. 13 2017
HiSAFE related content on Cseltmuseum Dec. 13 2017 HiSAFE related content on Cseltmuseum Dec. 13 2017
HiSAFE related content on Cseltmuseum Dec. 13 2017
 
CSELTMUSEUM post record August to December 2017
 CSELTMUSEUM post record August to December 2017 CSELTMUSEUM post record August to December 2017
CSELTMUSEUM post record August to December 2017
 
Piero Belforte related presentations on slideplayer.com july 12 2017
Piero Belforte related presentations on slideplayer.com july 12 2017Piero Belforte related presentations on slideplayer.com july 12 2017
Piero Belforte related presentations on slideplayer.com july 12 2017
 
Collection of Cselt related presentations on slideplayer.com by_Piero_Belfort...
Collection of Cselt related presentations on slideplayer.com by_Piero_Belfort...Collection of Cselt related presentations on slideplayer.com by_Piero_Belfort...
Collection of Cselt related presentations on slideplayer.com by_Piero_Belfort...
 

Último

Artificial Intelligence & SEO Trends for 2024
Artificial Intelligence & SEO Trends for 2024Artificial Intelligence & SEO Trends for 2024
Artificial Intelligence & SEO Trends for 2024D Cloud Solutions
 
Comparing Sidecar-less Service Mesh from Cilium and Istio
Comparing Sidecar-less Service Mesh from Cilium and IstioComparing Sidecar-less Service Mesh from Cilium and Istio
Comparing Sidecar-less Service Mesh from Cilium and IstioChristian Posta
 
UiPath Studio Web workshop series - Day 8
UiPath Studio Web workshop series - Day 8UiPath Studio Web workshop series - Day 8
UiPath Studio Web workshop series - Day 8DianaGray10
 
Bird eye's view on Camunda open source ecosystem
Bird eye's view on Camunda open source ecosystemBird eye's view on Camunda open source ecosystem
Bird eye's view on Camunda open source ecosystemAsko Soukka
 
IaC & GitOps in a Nutshell - a FridayInANuthshell Episode.pdf
IaC & GitOps in a Nutshell - a FridayInANuthshell Episode.pdfIaC & GitOps in a Nutshell - a FridayInANuthshell Episode.pdf
IaC & GitOps in a Nutshell - a FridayInANuthshell Episode.pdfDaniel Santiago Silva Capera
 
Designing A Time bound resource download URL
Designing A Time bound resource download URLDesigning A Time bound resource download URL
Designing A Time bound resource download URLRuncy Oommen
 
UiPath Platform: The Backend Engine Powering Your Automation - Session 1
UiPath Platform: The Backend Engine Powering Your Automation - Session 1UiPath Platform: The Backend Engine Powering Your Automation - Session 1
UiPath Platform: The Backend Engine Powering Your Automation - Session 1DianaGray10
 
20230202 - Introduction to tis-py
20230202 - Introduction to tis-py20230202 - Introduction to tis-py
20230202 - Introduction to tis-pyJamie (Taka) Wang
 
Building Your Own AI Instance (TBLC AI )
Building Your Own AI Instance (TBLC AI )Building Your Own AI Instance (TBLC AI )
Building Your Own AI Instance (TBLC AI )Brian Pichman
 
Salesforce Miami User Group Event - 1st Quarter 2024
Salesforce Miami User Group Event - 1st Quarter 2024Salesforce Miami User Group Event - 1st Quarter 2024
Salesforce Miami User Group Event - 1st Quarter 2024SkyPlanner
 
Nanopower In Semiconductor Industry.pdf
Nanopower  In Semiconductor Industry.pdfNanopower  In Semiconductor Industry.pdf
Nanopower In Semiconductor Industry.pdfPedro Manuel
 
Using IESVE for Loads, Sizing and Heat Pump Modeling to Achieve Decarbonization
Using IESVE for Loads, Sizing and Heat Pump Modeling to Achieve DecarbonizationUsing IESVE for Loads, Sizing and Heat Pump Modeling to Achieve Decarbonization
Using IESVE for Loads, Sizing and Heat Pump Modeling to Achieve DecarbonizationIES VE
 
Basic Building Blocks of Internet of Things.
Basic Building Blocks of Internet of Things.Basic Building Blocks of Internet of Things.
Basic Building Blocks of Internet of Things.YounusS2
 
UiPath Solutions Management Preview - Northern CA Chapter - March 22.pdf
UiPath Solutions Management Preview - Northern CA Chapter - March 22.pdfUiPath Solutions Management Preview - Northern CA Chapter - March 22.pdf
UiPath Solutions Management Preview - Northern CA Chapter - March 22.pdfDianaGray10
 
The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...
The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...
The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...Aggregage
 
VoIP Service and Marketing using Odoo and Asterisk PBX
VoIP Service and Marketing using Odoo and Asterisk PBXVoIP Service and Marketing using Odoo and Asterisk PBX
VoIP Service and Marketing using Odoo and Asterisk PBXTarek Kalaji
 
How Accurate are Carbon Emissions Projections?
How Accurate are Carbon Emissions Projections?How Accurate are Carbon Emissions Projections?
How Accurate are Carbon Emissions Projections?IES VE
 
KubeConEU24-Monitoring Kubernetes and Cloud Spend with OpenCost
KubeConEU24-Monitoring Kubernetes and Cloud Spend with OpenCostKubeConEU24-Monitoring Kubernetes and Cloud Spend with OpenCost
KubeConEU24-Monitoring Kubernetes and Cloud Spend with OpenCostMatt Ray
 
UiPath Community: AI for UiPath Automation Developers
UiPath Community: AI for UiPath Automation DevelopersUiPath Community: AI for UiPath Automation Developers
UiPath Community: AI for UiPath Automation DevelopersUiPathCommunity
 
UWB Technology for Enhanced Indoor and Outdoor Positioning in Physiological M...
UWB Technology for Enhanced Indoor and Outdoor Positioning in Physiological M...UWB Technology for Enhanced Indoor and Outdoor Positioning in Physiological M...
UWB Technology for Enhanced Indoor and Outdoor Positioning in Physiological M...UbiTrack UK
 

Último (20)

Artificial Intelligence & SEO Trends for 2024
Artificial Intelligence & SEO Trends for 2024Artificial Intelligence & SEO Trends for 2024
Artificial Intelligence & SEO Trends for 2024
 
Comparing Sidecar-less Service Mesh from Cilium and Istio
Comparing Sidecar-less Service Mesh from Cilium and IstioComparing Sidecar-less Service Mesh from Cilium and Istio
Comparing Sidecar-less Service Mesh from Cilium and Istio
 
UiPath Studio Web workshop series - Day 8
UiPath Studio Web workshop series - Day 8UiPath Studio Web workshop series - Day 8
UiPath Studio Web workshop series - Day 8
 
Bird eye's view on Camunda open source ecosystem
Bird eye's view on Camunda open source ecosystemBird eye's view on Camunda open source ecosystem
Bird eye's view on Camunda open source ecosystem
 
IaC & GitOps in a Nutshell - a FridayInANuthshell Episode.pdf
IaC & GitOps in a Nutshell - a FridayInANuthshell Episode.pdfIaC & GitOps in a Nutshell - a FridayInANuthshell Episode.pdf
IaC & GitOps in a Nutshell - a FridayInANuthshell Episode.pdf
 
Designing A Time bound resource download URL
Designing A Time bound resource download URLDesigning A Time bound resource download URL
Designing A Time bound resource download URL
 
UiPath Platform: The Backend Engine Powering Your Automation - Session 1
UiPath Platform: The Backend Engine Powering Your Automation - Session 1UiPath Platform: The Backend Engine Powering Your Automation - Session 1
UiPath Platform: The Backend Engine Powering Your Automation - Session 1
 
20230202 - Introduction to tis-py
20230202 - Introduction to tis-py20230202 - Introduction to tis-py
20230202 - Introduction to tis-py
 
Building Your Own AI Instance (TBLC AI )
Building Your Own AI Instance (TBLC AI )Building Your Own AI Instance (TBLC AI )
Building Your Own AI Instance (TBLC AI )
 
Salesforce Miami User Group Event - 1st Quarter 2024
Salesforce Miami User Group Event - 1st Quarter 2024Salesforce Miami User Group Event - 1st Quarter 2024
Salesforce Miami User Group Event - 1st Quarter 2024
 
Nanopower In Semiconductor Industry.pdf
Nanopower  In Semiconductor Industry.pdfNanopower  In Semiconductor Industry.pdf
Nanopower In Semiconductor Industry.pdf
 
Using IESVE for Loads, Sizing and Heat Pump Modeling to Achieve Decarbonization
Using IESVE for Loads, Sizing and Heat Pump Modeling to Achieve DecarbonizationUsing IESVE for Loads, Sizing and Heat Pump Modeling to Achieve Decarbonization
Using IESVE for Loads, Sizing and Heat Pump Modeling to Achieve Decarbonization
 
Basic Building Blocks of Internet of Things.
Basic Building Blocks of Internet of Things.Basic Building Blocks of Internet of Things.
Basic Building Blocks of Internet of Things.
 
UiPath Solutions Management Preview - Northern CA Chapter - March 22.pdf
UiPath Solutions Management Preview - Northern CA Chapter - March 22.pdfUiPath Solutions Management Preview - Northern CA Chapter - March 22.pdf
UiPath Solutions Management Preview - Northern CA Chapter - March 22.pdf
 
The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...
The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...
The Data Metaverse: Unpacking the Roles, Use Cases, and Tech Trends in Data a...
 
VoIP Service and Marketing using Odoo and Asterisk PBX
VoIP Service and Marketing using Odoo and Asterisk PBXVoIP Service and Marketing using Odoo and Asterisk PBX
VoIP Service and Marketing using Odoo and Asterisk PBX
 
How Accurate are Carbon Emissions Projections?
How Accurate are Carbon Emissions Projections?How Accurate are Carbon Emissions Projections?
How Accurate are Carbon Emissions Projections?
 
KubeConEU24-Monitoring Kubernetes and Cloud Spend with OpenCost
KubeConEU24-Monitoring Kubernetes and Cloud Spend with OpenCostKubeConEU24-Monitoring Kubernetes and Cloud Spend with OpenCost
KubeConEU24-Monitoring Kubernetes and Cloud Spend with OpenCost
 
UiPath Community: AI for UiPath Automation Developers
UiPath Community: AI for UiPath Automation DevelopersUiPath Community: AI for UiPath Automation Developers
UiPath Community: AI for UiPath Automation Developers
 
UWB Technology for Enhanced Indoor and Outdoor Positioning in Physiological M...
UWB Technology for Enhanced Indoor and Outdoor Positioning in Physiological M...UWB Technology for Enhanced Indoor and Outdoor Positioning in Physiological M...
UWB Technology for Enhanced Indoor and Outdoor Positioning in Physiological M...
 

A simultaneous two-way digital transceiver on a single line

  • 1. - 250 - ESSCIRC'85 RTB: A Full-Duplex ECL Transceiver For Wideband Digital Systems. Piero Belforte Vanni Poletto Mario Sartori - - CSELT (Centro Studi e Laboratori Telecomunicazioni) 1014B Torino (Italy), via G. Reiss Romoli 274, Tel. 39-11-21691 Summary This paper deals with the design of a low cost ECL bipolar compatible I.C performing the function of four balanced full-duplex transceivers particularly suitable for interconnections long up to several tens of meters in digital systems. One of the most interesting applications of this circuit is in the field of wideband digital switching (up to 100 Mbit/sec) where the amount of two-way internal connections can be very high, [l] More precisely when bidirectional video communications are concerned (as in the case of the digital switching of video telephony signals) the use of this component virtually halves the wiring cost. Other applications include narrow band (up to 2 Mbit/sec) digital switching systems where it is possible to achieve great saving in cabling cost or to allow the designers to implement interesting diagnosis and signalling schemes inside the exchange.[2] Obviously his application range is not bounded to these fields but covers all the situations where two-way communication implying the use of standard receiver/transmitter pairs is needed. The functional behaviour of RTB is shown in fig. 1: Ct is an ECL driver with a low output inpedance, Ip is a common mode current source, Ro is the line characteristic resistance, A1(A2) are linear amplifiers, Cr is a differential to single ended ECL translator. (.) Patents pending
  • 2. - 251 - When two transceivers sending data through the same line, the signal at are both end of the line is a superposition of the one transmitted from the local terminal and the one received from the remote terminal. The line signal swing is a bit larger than the standard ECL but down-shifted about .8 V. The circuit subtracts from the line signal the contribution due to trasmitter, taking into account the 6 dB attenuation caused by the line impedance matching. In ideal conditions (lossless cable and negligible output impedance of the driver), it is easy to show that, if the gain of Al is a half of the gain of A2, a complete cancellation of the transmitted signal occurs. In such a way the output translator Cr has the function of restoring the ECL level compatibility. As the circuit recovers the incoming signal wave, it is easy to gain information about an abnormal state of the link (cut or shorted). This feature also supplies a very simple method for testing the circuit; in fact, when the line is open, the signal decoded at the receiving side of the tranceiver is equal to the transmitted one, while when it is shorted the complement of the transmitted signal can be found at the output. Therefore, connecting both open and shorted the four tranceivers' line outputs, allows to check the correct behaviour of the device. chip four different functions are present, each one working in a fully In the independent mode, so attention must be paid to avoid crosstalk among them. For this reason a careful design was made of the common bias circuit to obtain an efficient decoupling. The main goal of thedesign was to achieve the best trade-off between speed and power dissipation. For this reason a new low dissipation switched-load line driver (*) suitable for ECL circuitry was developed, [fig. 2] The power consumption of the drivers is externally programmable according to bit-rate requirements and length of the cable interconnection; this is obtained through an internally built voltage reference and an external programming resistor. In the chip's architecture the bias circuit is shared by the four transceivers and a
  • 3. - 252 - power saving is gained in it owing to the availability of complementary current mirrors and amplifiers. (*) The I.C. designed following both traditional and new methodological was approaches. In particular the optimization of the circuit from the point of view of speed was carried out using advanced characterization and simulation techniques. The choice of the sizes and geometries of transistors making up the main circuit blocks (current switches, buffers, etc.) was the consequence of their time-domain reflectometer (TDR) characterization. The TDR responses have been obtained from a set of standard kit-parts available on SGS LLV process. From these TDR responses very accurate macromodels of circuit blocks are obtained using fitting programs. The very close integration between computerized measurements and simulation tools allows the designer to obtain very quickly and easily the optimized parameters of macromodels. [fig. 3] These macromodels and their related parameters are then used to simulate the internal behaviour, mainly concerning critical paths, in the integrated circuit. A similar technique was also utilized for pin level electrical characterization of the whole circuit. The real world operation where two similar tranceivers are interconnected through an external lossy cable was then analyzed. In this case the actual cable is directly modeled by its time-domain scattering parameters. Suitable simulation programs [3] utilize both I.C. and cable models for the analysis of situations which are not covered by standard simulation aids. The results of these evaluations for various bit-rates and cable lengths are shown in the paper [fig. 4]. Chip's photograph and sizes are shown in Fig. 5. Finally the main features of the implemented chip are given including electrical performances [fig. 6] and actual measurements in real operating conditions, [fig. 7] The RTB is now inserted as standard component among telecom I.Cs by S.G.S ATES.
  • 4. - 253 - Acknowledgments The authors wish to thank particularly Dr. Siligoni and Dr. Garue of S.G.S ATES for their useful advices during the developement of the circuit. Bibliography [l] Enzo Garetti Piero Belforte Luciano Gabrieili "New switching techniques for wideband and ISDN environments" International Switching Symposium'84 (ISS '84) Florence [2] Piero Belforte Enzo Garetti "A new generation of LSI switching networks" FORUM 'B3 Geneva. - [3] Piero Belforte Bruno Bostica Giancarlo Guaschino 'Time domain simulation of lossy interconnections using wave digital networks" International Symposium on Circuits and Systems (ISCAS '82) Roma, May 10-12, 1982
  • 5. - 254 - snfeUb b '-|r.o)¿ -^O-i Po §1' et.i'a Fig. 2 - Switched current load f Line.driver. -TWHE J/77Ef? (X) vs. DATA RATE (L=4m-24m FULL DUPLEX) í GAMMA (my) Mp«) 400pl I fSrtflV r(oo).r(R^).-7IOmS equivalent T-2BB NO/VIV circuit response p(Mbiu<.; Fig.3 - Fitting of the emitter follower T.D.R. response Fig. 4 - Time jitter computer evaluation for different using a macromodel. interconnection lengths (100 balanced ribbon cable).
  • 6. - 255 - - Main electrical characteristics. - Voltage supply 5V +_ lou - Power consumption 660 mW - Input and output levels ECL 10K canpatibile - Typical Input-output delay time (transmitter + receiver) 7 ns IÎ&L _7 . Receivers ' output Eye patterns in real operating ccnditlans. (TVo functions connected through 8 meter ribbon cable) Upper : 50 M bit/sec. Lower : 100 Kbit/sec uncorrelated. Fig. 5 - Chip's photograph (device area 3.2 mm2 pad area = 25%)