1. Roshan Barua Project Synopsis
Development of Floating Point Processor in FPGA
using VHDL for control of BLAC servomotor
Introduction:
The division of Remote Handling and Robotics (DRHR) at the Bhabha Atomic Research
Centre has developed a Tele-Robot which finds applications in remote handling operations.
This robot uses BLAC servomotors for its joint actuations. Presently, such motors are
controlled via as ASIC. We have now developed a Floating Point processor in FPGA using
VHDL. The Floating Point Processor will form a part of an FPGA based controller for these
BLAC servomotors. The task included the study of IEEE Floating Point Standard & its
implementations using VHDL. This is first implemented using a development IDE from Xilinx.
Subsequently we have programmed the FPGA using the VHDL code and tested its functional
operations.
Aim & Objective:
To develop a arithmetic matrix co-processor which utilises floating point inputs for calculation
of space vector control implemented by the Telerobot
Methodology:
The Project fundamentally consisted of three assignments.
Detailed Study of the Telerobot
The Telerobot consists of two identical electrically connected articulated arms: the master arm
and the slave arm. The force reflecting Tele-robot represents a new generation of remote
handling technology with advanced features like position control of the slave arm in world
coordinates, indexing in world coordinates, scaling of slave motion, tremor removal,
constrained motion, teach and playback mode, interactive robot mode etc. The Telerobot is
provided with six Degrees of Freedom and has a payload of 25 kg. It has a maximum reach of
1.2 m and the gripper opening is 100 mm. The force reflection ratio varies from 0 to 1 and the
maximum force reflected is 8 kg.
Intensive Research on IEEE Floating point standards, study of FPGA’s and Servomotors
Normally FPGAs comprise of -
 Programmable logic blocks which implement logic functions
 Programmable routing that connects these logic functions
 I/O blocks that are connected to logic blocks through routing interconnect and that
make off-chip connections.
The ‘programmable/reconfigurable’ term in FPGAs indicates their ability to implement a new
function on the chip after its fabrication is complete. The reconfigurability/ programmability of
an FPGA is based on an underlying programming technology, which can cause a change in
behaviour of a pre-fabricated chip after its fabrication. Study in IEEE standards-786 was
pivotal for development of a floating point co-processor.
Development of Floating Point Co-processor
To overcome device size restriction, subsequent single-FPGA implementations of IEEE 754
standard employed serial arithmetic or avoided features, such as supporting gradual
underflow, which are expensive to implement was used. In this project, a high-speed
IEEE754-compliant 32-bit floating point arithmetic unit designed using VHDL code has been

2. presented and all operations of addition, subtraction, multiplication and division have been
tested on Xilinx and verified successfully. Floating point numbers are one possible way of
representing real numbers in binary format; the IEEE 754 [11] standard presents two different
floating point formats, Binary interchange format and Decimal interchange format. This paper
focuses only on single precision normalized binary interchange format. In the IEEE 754 single
precision binary format representation; it consists of a one bit sign (S), an eight bit exponent
(E), and a twenty three bit fraction (M) or Mantissa.
32 bit Single Precision Floating Point Numbers IEEE standard are stored as:
S EEEEEEEE MMMMMMMMMMMMMMMMMMMMMM
S: Sign – 1 bit, E: Exponent – 8 bits M: Mantissa – 23 bits Fraction
The ‘exponent base’ is 2** ((maximum exponent/2)–1) and ‘Fraction’ is always a number less
than one. The final task was to build a Matrix Co-processor which can build and process
floating point numbers in a matrix format to perform basic arithmetic tasks such as Addition,
Subtraction etc. and display the output in the desired IEEE format.
Block diagram:
Conclusion:
 Initial testing of matrix engine using basic integers and floats inputs were carried out.
 The floating point matrix co-processor necessary for vector space control of the
Telerobot was implemented and its results were noted.
 The entire project was carried out on a Spartan3E FPG
 A kit with further scope to implement on CPLD.