Session 02 v.3

• Click to edit Master text styles
– Second level
• Third level
– Fourthg i t a l D e s i g n u s i n g V H D L
D i level
Session Two
» Fifth level

Introduced by

Cairo-Egypt

Version 03 – June 2012 1

about Start Group

Mahmoud Abdellatif
– Second level
Alaa Salah Shehata
Mohamed level
• Third Salah
Mohamed Talaat
– Fourth level
» Fifth level
start.courses@gmail.com www.slideshare.net/StartGroup

www.facebook.com/groups/start.group

www.startgroup.weebly.com Start.courses@gmail.com

+ 02 0122-4504158 M.A www.youtube.com/StartGroup2011
+ 02 0128-0090250 A.S

Session Two 2

Refresh Your Memory

5
X1
Y
• Click to this code
Find the 7 errors inedit Master text styles X2
5
AND_GATE
5

– Second level
library IEEE;
• Third level
Entity 5_AND_GATE is
Port ( – Fourth level
X1 : in std_logic(5 downto 0 );
» Fifth level
X2 : in std_logic(5 downto 0 );
Y : out std_logic(5 downto 0 );
);
END 5_and_gate;
Refresh
Architecture Behave of AND_GATE_5 IS Your Memory
Slides
Y <= X1 AND X2 ;
END 5_AND_GATE;

Session Two 3

Refresh Your Memory [Solution]

5
X1
Y
• Click to edit Master text styles X2 5
AND_GATE
5

– Second level
library IEEE;
• Third level
USE ieee.std_logic_1164.all; -- 1 Use Package to define
operations on std_logic data type
– Fourth
Entity AND_GATE is level -- 2 Don’t Start with number
Port (
» Fifth level
X1 : in std_logic_vector(4 downto 0 ); -- 3 wrong data type
X2 : in std_logic_vector(4 downto 0 ); -- 4 4 downto 0
Y : out std_logic_vector(4 downto 0 ) -- 5 No ;
);
END AND_GATE;

Architecture Behave of AND_GATE IS -- 6 wrong entity name
Begin --7 Reserved word
Y <= X1 AND X2 ;
END behave ; -- 8 architecture name

Session Two 4

Outline

– Second level
• Third level
Data Objects : Signals

VHDL Statements
- Sequential Statements
2
– Fourth level
- What is Process
» Fifth level - IF Statement
- CASE Statement
- Combinational Logic
- Sequential Logic

Mini Project no.1 ALU

Session Two 5

Outline

– Second level Data Objects : Signals

• Third level VHDL Statements
– Fourth level - Sequential Statements
- What is Process
- CASE Statement
- Sequential Logic


Session Two 6

Signals

Signals used to connect between systems or connect components inside a system
Signals represent physical wiring in hardware
– Second level
Types of signals
• Third level
-- External Signals
– Fourth level Inout ports
-In,Out and
-Internal connections in structural Description discussed later
-- Internal Signals level
» Fifth
-Connect devices inside the block
-Used for Intermediate calculations
Note
We use Internal Signals for:
- Avoid illegal port usage situations like Read Output port
- Internal Connections ‘wiring’

Session Two 7

Internal Signals

Signal Declaration
– Second level
architecture <arch_name> of <entity_name> is
• Third level
-- architecture declarations
signal <sig_name> : <sig_type>;
– Fourth level.
.
begin » Fifth level
<Architecture body>

End <arch_name> ;

Note
we don’t define a mode for internal signals

Session Two 8

Example 05

NAND Gate
– Second level
LIBRARY ieee;
USE ieee.std_logic_1164.all;
A
E D
ENTITY • Third
NAND_GATE ISlevel
port ( A,B B
C
– Fourth STD_LOGIC;
: in
level
: in STD_LOGIC;
D : » Fifth level
out STD_LOGIC C
);
END ENTITY NAND_GATE ;

ARCHITECTURE behave OF NAND_GATE IS

SIGNAL E : std_logic;

BEGIN
E <= A and B ;
D <= E and C ;
END behave;

Session Two 9

Exercise 01

Write VHDL code for this logic circuit
A – Second level
• Third level G
B – Fourth level
» Fifth level

C

F
D

Session Two 10

Exercise 01 [Solution]

Write the VHDL code for this logic circuit
LIBRARY ieee; A
– Second level
SIG_1 G
ENTITY NAND_GATE IS B
• Third level
port ( A,B,C,D : in STD_LOGIC;
G,F
);
– Fourth STD_LOGIC
: out
level
END ENTITY NAND_GATE Fifth level
» ; C SIG_2
ARCHITECTURE behave OF NAND_GATE IS

SIGNAL SIG_1 : std_logic; F
SIGNAL SIG_2 : std_logic; D
BEGIN
SIG_1 <= A and B ;
SIG_2 <= SIG_1 and C ;
F <= SIG_2 and D ;
G <= SIG_1 ;
END behave;
Session Two 11

Outline


- What is Process
- CASE Statement
- Sequential Logic


Session Two 12

Combinational Vs. Sequential logic

in any digital system we can divide the circuits into two types :
– Second level
• Third level
Combinational logic circuits
implement Boolean functions, so the output in this circuits is
function only on– Fourth level are not based on previous
their inputs, and
outputs.
» Fifth level

Sequential circuits
compute their output based on input and state(previous
outputs), and that the state is updated based on a clock.

Session Two 13

Concurrent & sequential statements

VHDL has concurrent statements and sequential statements

– Second level
•Concurrent statements are executed in parallel w.r.t each other.
Process statement
• Third level
Assign statement
With – select
When– Fourth level
– else
» Fifth level
•Sequential statements are executed in sequence w.r.t each other.
Sequential statements should be written inside a “process”
If statement
Case statement
loop statements
Wait and Null statement

Session Two 14

Process

-What is a Process
Process allows writing sequential statements within concurrent
environment
– Second level
Process is like a container that include the sequential statements
Process declaration
• Third level
process (sensitivity list)
begin – Fourth level
sequential statements ;
» Fifth level
end process ;

Note
<sensitivity_list>:
List of signals/input ports that cause the process to be executed
whenever there is a change in their values

Session Two 15

Process

Architecture behave of comb_ct is
Begin
process (x,y)
begin
– Second level
z <= x and y;
• Third or y;
h <= x
level
t <= x xor y;
– Fourth level
…

end process;» Fifth level
End behave ;

Statements inside a “process” are read sequentially and executed when the process suspends
(“end process” is reached)

very important note:
Process executed one time then become ready for a change on its sensitivity list.
How is this statement differs from z<= x and y;

Session Two 16

IF Statement

Executes a list of sequential statements when the corresponding condition evaluates to true

– Second level
V.IMPORTANT ROLE
The branches order is important as they imply a priority

Syntax
• Third level
– Fourth level
» Fifth level
If <condition> then
-- list of sequential statements
elsif <condition> then
else
end if;

<condition> Boolean expression that evaluates to either TRUE or FALSE

Session Two 17

CASE Statement

Makes several conditions on the same signal
Syntax

– Second level
case <expression> is
• Third level
when <choice> =>
when <choice> – Fourth level
=>
when others => » Fifth level
end case;

<expression> can be a signal [or a variable (discussed later)]
<choice> constants representing one of possible <expression> values.

V.IMPORTANT ROLE
-“When others” is a must if not all values of <expression> are covered
- Each branch of a Case statement can have any number of sequential statements
Session Two 18

Outline


- What is Process
- CASE Statement
- Sequential Logic


Session Two 19

Example 06

Logic Gate
LIBRARY ieee;
– Second level A
ENTITY logic_gate IS C
Logic Gate
port ( a, b
C • Third level
: in std_logic;
: out std_logic; B
Sel : in std_logic);
– Fourth level
END ENTITY logic_gate;
» Fifth level
ARCHITECTURE behave OF logic_gate IS
BEGIN
process ( What is sensitivitySel !!
a, b, list ) Sel
begin
if (Sel= '1') then Operation = 1  a and b
C <= a and b; Operation = 0  a or b
elsif (Sel = „0') then '
C <= a or b;
else
C <= „Z‟;
end if;
end process;
END ARCHITECTURE behave;
Session Two 20

Example 07

Comparator
LIBRARY ieee;
– Second level
ENTITY comparator IS
port( a, b : in std_logic_vector(7 downto 0);
c
• Third level
: out std_logic_vector(1 downto 0);
);
END ENTITY; – Fourth level
ARCHITECTURE behave OF comparator IS
BEGIN » Fifth level
process (a, b) A
begin C
if (A = B ) then -- equality Comparator
c <= "00";
elsif (A > B) then -- greater than
B
c <= "01";
elsif (A < B) then -- greater than
c <= "10";
A=B C=“00”
else -- covers other cases
c <= “ZZ";
A>B C=“01”
end if; A<B C=“10”
end process;
END ARCHITECTURE; Session Two 21

Example 08

4 x 1 Multiplexer
Architecture rtl of mux_case is
– Second level A
begin
process (a,b,c,d,sel) B F
begin • Third level C
Case sel is
When "00" => – Fourth level D
f <= a;
When "01" =>
» Fifth level
f <= b;
When "10" => Sel
f <= c;
When "11" =>
f <= d;
when others => -- is "when others“ a must?
f <= „Z‟; Do we need all these signals? On
End case; sensitivity list ??
End process;
End architecture;

Session Two 22

Lab 01

• Click to edit2 Master text styles
Title:
Simulation of a X 4 Decoder on ModelSim
– Second of a simple 8-bits Comparator
Simulation
level
Goal: • Third level
 Creating new project on ModelSim
 – Fourth a combinational circuit
Simulation oflevel
» Fifth level

Tutorial [1]
Slides

Session Two 23

Lab 01

2 X 4 Decoder

– Second level
Architecture rtl of dec is
begin
a f
process (a)
begin • Third level
Case a is
When "00" =>
– Fourth level
f <= “0001”;Fifth level
»
When "01" =>
f <= “0010”;
When "10" =>
f <= “0100”;
When "11" =>
f <= “1000”;
when others =>
f <= “ZZZZ”;
End case;
End process;
End rtl ;

Session Two 24

Outline


- What is Process
- CASE Statement
- Sequential Logic


Session Two 25

Sequential Circuits

– Second level
•
Clock period Third level
– Fourth level
A digital clock signal is a square wave voltage.
In complex circuits a clock withlevel frequency is used for timing.
» Fifth a fixed
To store and pass the data or digital signals through, some specific gates are used which
are called latches or flip-flops. These are some kind of memory that store their input
over their output by a specific level or edge of the clock.

Asynchronous Operation
don’t wait clock
Synchronous Operation
wait clock to get an input and to produce an output

Session Two 26

D-Flip Flop

Reset Clk Enable Q+

D 1 - - 0
Q
– Second level 0 No rising_edge - Q
Reset 0 Rising_edge 0 Q
• Third level
D_FF
0 Rising_edge 1 D
enable – Fourth level
» Fifth level
clk

Clock period

Asynchronous reset
Synchronous enable
Session Two 27

D-Latch

Reset Clk Enable Q+

D 1 - - 0
Q
– Second level 0 0 - Q
Reset 0 1 0 Q
• Third level
D_Latch
0 1 1 D
enable – Fourth level
» Fifth level
clk

Clock period

Asynchronous reset
Synchronous enable
Session Two 28

D-Latch vs D-Flip Flop

– Second level
With a D-latch working on High level of clock , a signal can’t propagate through until the
clock is high .
• Third level
With a rising edge D-Flip-flop, the signal only propagates through on the rising edge.
– Fourth level
» Fifth level
Clock
D

Q

D_Latch D-Flip Flop

Session Two 29

Example 09

Simple D-FF
D
Library ieee;
– Second level
use ieee.std_logic_1164.all; Q
D_FF
• Third level
Entity d_ff is
Port( D, clk : in std_logic;
Q – Fourth std_logic );
: out level
end entity;
» Fifth level
Architecture behav of d_ff is
clk
Begin
process(clk)
begin
if rising_edge(clk) then
Q <= D;
end if; rising_edge() : function defined for std_logic type
end process; Used to detect rising edge of clock

end behav;

Session Two 30

Example 10

D-FF with asynchronous reset
Library ieee; D
– Second level
use ieee.std_logic_1164.all; Q
Entity d_ff is
• Third level Reset D_FF
Port( d, clk, rst : in std_logic;
Q : out std_logic);
end entity;
– Fourth level
Architecture behav » Fifth level
of d_ff is

Begin
process(clk, rst)
clk
begin
If (rst = '1') then
Q <= '0';
elsif rising_edge(clk) then Since rst has higher priority over the clk edge
Q <= d; then, We put it on sensitivity list
end if;
end process; We have now a D Flip Flop with asynchronous reset

end behav;
Session Two 31

Example 11

D-FF with asynchronous reset and clock enable
Library ieee;
Reset
1
Clk
-
Enable
-
Q+
0
use ieee.std_logic_1164.all;
– Second level
Entity d_ff is
0 No rising_edge - Q
0 Rising_edge 0 Q

Q
• Third level
Port( d, clk, rst,en : in std_logic;
: out std_logic);
0 Rising_edge 1 D

end entity; – Fourth level
Architecture behav » Fifth level
of d_ff is
Begin
process(clk, rst)
begin
If (rst = '1') then
Q <= '0';
Enable has lower priority w.r.t the clk edge
elsif rising_edge(clk) then
So we don’t put it in sensitivity list as it has no
If (en = '1') then value and will slow the simulation
Q <= d;
end if;
end if; We have now a D Flip Flop with asynchronous
end process; reset and synchronous enable
end behav;
Session Two 32

Example 12

D_Latch (positive level)
library ieee;
Reset
1
Clk
-
Q+
0
use ieee.std_logic_1164.ALL;
– Second level
entity d_ff is
0 0 Q
0 1 D
port( • Third level
clk,reset,enable: in std_logic;
d: in – Fourth level
std_logic;
q: out std_logic);
end d_ff; » Fifth level
architecture Behavioral of d_ff is
begin
process(clk,reset,d)
begin
Latch depend on input every time it changes
if reset = '1' then
while clk =‘1’ so if clk still =‘1’ and input changes
q<= '0'; process should be triggered
elsif clk = '1' then So, d on sensitivity list
q<= d;
end if;
end process;
end Behavioral;
Session Two 33

Start Notes [Synthesis Notes]

• Click to edit Master text D-FF coding
Example of illegal styles
Legal in VHDL but not synthesized
– Second level
D-FF coding rules
if reset = '1' then
• Third level
FF is a the basic memory q <= '0';
Elsif rising_edge(clk)then
unit . We need –a Fourth level
lot to
q <= d;
register the data. Some Elsif d = ‘1’ then
» Fifth level
rules should be done on q <= not d;
flip flop to be written in end if;
the right way. You need
only to keep in your mind this code also not synthesized
the D-FF code, Latches are
if enable = '1' then
not preferred to be used to if rising_edge(clk)then
avoid glitches. q <= d;
end if;
end if;

Session Two 34

Start Notes [Synthesis Notes]

• Click to edit MasterRegister D-FF coding
Example oftext styles
illegal
or latch
– Second level
• Third level Reg : Process (clk)
begin
– Fourth level if clk = '1' then
q <= d;
» Fifth level if;
end
End process reg;

The Answer is

not latch as d is not in sensitivity list
not register (no clock edges detected)

Session Two 35

Start Notes [Simulation Notes]

Example of common errors
– Second level
Read Errors
forget end if ; awhen you use else if pattern
instead of elsif pattern
• Third level
You Should read the error
– Fourth
first , don’t be disturbed. level
Compilers always give » Fifth level
you
if reset = '1' then
the position where the q<= '0';
error is and also may help Else if clk = '1' then
you know the reason of q<= d;
the error, you may also end if;
search the error on the
internet .

Session Two 36

Start Notes [Simulation Notes]

– Second level
Cover all Cases
• Third level
To make sure that your
– Fourth
code is working well, cover level
all cases that your code go
» Fifth level
inside. For example, in
many cases you may see ‘X’
values that mean there is
multiple drivers to a
specific signal . Or ‘U’ value
for unitialized signals

Session Two 37

Outline


- What is Process
- CASE Statement
- Sequential Logic


Session Two 38

Mini Project

• ALU Arithmetic Logic UnitMaster text styles
-
Click to edit
– Second level
It is a circuit capable of executing both kinds of operations, arithmetic as well as logical.
Its operation is described next slide as follow :
• Third level
The output (arithmetic or logical) is selected by the MSB of sel
The specific operation is selected by sel’s other three bits.
– Fourth level
» Fifth level
A(7:0) Logic
B(7:0) Unit

C(7:0)

Arithmetic
Unit
Cin
SEL(3:0)

Session Two 39

Mini Project
Sel Operation Function Unit
0000 Y<= a Transfer A

• Click to edit MasterY<= a+1 styles A
0001 text Increment
0010 Y<= a-1 Decrement A
– Second level
0011 Y<= b Transfer B
0100 Y<= b+1 Increment A
• Third level Arithmetic
0101 Y<= b-1 Decrement A
– Fourth level
0110 Y<= a+b Add a and b
» Fifth level
0111 Y<= a+b+cin Add a and b and carry
1000 Y<= not a Complement a
1001 Y<= not b Complement b
1010 Y<= a AND b AND
1011 Y<= a OR b OR
Logic
1100 Y<= a NAND b NAND
1101 Y<= a NOR b NOR
1110 Y<= a XOR b XOR
1111 Y<= a XNOR b XNOR
Session Two 40

Mini Project

- Required
-VHDL code of this ALU
-Verify functionality using ModelSim (Waveforms required)
– Second level
-Use ieee.std_logic_arith.all; package in your design

- •
Deadline Third level
-After Next session
– Fourth level
» Fifth level
A(7:0) Logic
B(7:0) Unit

C(7:0)

Arithmetic
Unit
Cin
SEL(3:0)

Session Two 41

Assignment 02

– Second level
Write a code describing a 8-bit Register

• Third level
Grouping Eight D_FF translated into a Register. Describe it with two outputs Q and inverted Q
– Fourth level
» Fifth level D
Q
Reset Register
Q’

clk

Session Two 42

Summary

- Signals are used for internal wiring.
- – Second level
Concurrent statements and Sequential statements are statements types of VHDL.
- IF ELSIF ELSE and CASE statements should be written inside PROCESS
- Process• Third level that should contain all signals have priority than clock.
has sensitivity list
- D-FF is the main memory unit in Digital logic design.
– Fourth level
» Fifth level

Examples Exercises Labs
5-12 1 1

Session Two 43

Time for Your Questions

– Second level
• Third level
– Fourth level
» Fifth level

Session Two 44

Download Session 02 Files

Read Session- 2 Examples carefully to be ready for the next session’s LAB QUIZ

–Lab 01 www.startgroup.weebly.com/vhdl-examples.html
Second level
• Third level
– Fourth level
Reserved Words of VHDL
www.startgroup.weebly.com/vhdl-examples.html
» Fifth level

Related Sessions

Tutorial 1 Refresh Your
Memory 1

Session Two 45

Take Your Notes
Print the slides and take your notes here
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See You Next Session .. Don’t miss


Thank
– Second level
• Third level
– Fourth level

You
» Fifth level

Session 02 v.3

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