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Computer Architecture Grade 12
Introduction ,[object Object],[object Object],[object Object],[object Object],[object Object]
Regulating activities on the Motherboard… The System Clock Quartz Crystal Overclocking Using BIOS settings in your “blue screen” boot-up menu…
CPU Speed and Performance ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Pipelining?
Pipelining… Pipelining, a standard feature in RISC processors, is much like an assembly line.
The Smarter Approach… That said,  Pipeline Processing  is a method of processing where the processor is able to read new instructions from memory before the instruction that is being processed is completely processed…
Another example:
Problems with Pipelining Exercise… CISC and RISC CPU  Designs
CISC and RISC Processors C omplex  I nstruction  S et  C omputing R educed  I nstruction  S et  C omputing Vs. Commands are same length as one clock pulse/ cycle (synchronized with the system clock)  Commands are not synchronized – bad for pipelining… Extra space is used for logic and maths circuitry. Therefore much faster. More space is taken up on the chip for decoding complex instructions. Processing is faster Processing is slower Example: X = (4 + 3) + (4 +3) + (4 + 3)  Harder for programmers Example: X = 4 x 3 Easy for programmers Simple instructions for single operations Complex Instructions for multiple operations RISC CISC
GRADE 12: Group Work ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

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Computer architecture 12

  • 2.
  • 3. Regulating activities on the Motherboard… The System Clock Quartz Crystal Overclocking Using BIOS settings in your “blue screen” boot-up menu…
  • 4.
  • 5. Pipelining… Pipelining, a standard feature in RISC processors, is much like an assembly line.
  • 6. The Smarter Approach… That said, Pipeline Processing is a method of processing where the processor is able to read new instructions from memory before the instruction that is being processed is completely processed…
  • 8. Problems with Pipelining Exercise… CISC and RISC CPU Designs
  • 9. CISC and RISC Processors C omplex I nstruction S et C omputing R educed I nstruction S et C omputing Vs. Commands are same length as one clock pulse/ cycle (synchronized with the system clock) Commands are not synchronized – bad for pipelining… Extra space is used for logic and maths circuitry. Therefore much faster. More space is taken up on the chip for decoding complex instructions. Processing is faster Processing is slower Example: X = (4 + 3) + (4 +3) + (4 + 3) Harder for programmers Example: X = 4 x 3 Easy for programmers Simple instructions for single operations Complex Instructions for multiple operations RISC CISC
  • 10.