This document discusses power integrity challenges in modern PCB design and introduces an EDA methodology for concurrent power integrity simulation throughout the PCB design process. It covers topics like IC switching current needs, power distribution system impedance behavior, decoupling capacitor placement considerations, and examples of using power integrity simulation to optimize PCB designs. The methodology aims to identify power integrity issues earlier to improve quality and reduce costs compared to traditional verification later in the design flow.

1. Improve PCB Quality and Cost with
Concurrent Power Integrity Analysis
Ralf Brüning, Product Manager High-Speed Design
Solutions/Senior Partner
Humair Mandavia, Senior Technical Marketing Manager

2. Agenda
• Increasing challenges with power
distribution systems on modern
high-speed PCBs
• The problem:
– IC input impedance behavior
– Resonance behavior of PDS
– Role of decoupling capacitors
• EDA methodology for concurrent
power integrity simulation
throughout PCB design process
• Summary/Outlook
PCB Design
Problems
PCB Design
Problems
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3. Traditional Verification Disciplines
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4. Power Distribution Systems
DC Voltages are not equally distributed and not considered ideal over
copper planes
3.27V
3.3V
3.25V
Loads
Voltage
Source
Example: 3.3V Power Distribution System
“Voltage drops” occur on the copper area and within the vias
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5. Basic Electrical Concepts
I
V
• Resistors dissipate energy
– Resistance = Voltage / Current (R = V / I) R
– Voltage = Current  Resistance (V = I  R)
I
• Capacitors store energy in an electric field VV
V
– Charge = Capacitance  Voltage (q = CV) +
C
– Current (q / time) = C  (V / t) (I = C  V / t)
– Power plane over ground plane is a great capacitor!
I / t V
• Inductors store energy in a magnetic field +
– Voltage = Inductance  (I / t) (V = L  I / t)
L
– Oppose current changes with a voltage
– Inductive kick: pull the plug on a vacuum cleaner
when it’s running!
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6. Voltage Supply for ICs:
Power Distribution System (PDS)
• The power distribution system (PDS) will provide voltages and charge to the ICs
on a PCB
• Charge on the board must be supplied over a broad frequency range:
- Low frequency activities (we still have them)
- In MHz range for CPU-peripheral interfaces
- At the clock frequency (several hundreds of MHz)
- Provide a low impedance path for parasitic voltages at various
harmonics of the clock
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7. Power Plane Resonances Impedance
Behavior
• Power Plane Pair input impedance vs. frequency shows varied behavior
in different ranges:
Capacitive
behavior
(“DC”)
Z=1/jC
2D-Resonances
Continue to
infinity…
LC-Series
resonance of the Inductive
plate capacitor behavior of the
with the plane’s plane
inductance
Local dependency of Plane Impedance
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8. Power Plane Pairs Concerns
• Power plane pairs are used to provide the switching current to the ICs in a
higher frequency range where decoupling capacitors cannot work effectively
(f>20-50 MHz).
• A constant low impedance is required in a wide frequency range between the
fundamental clock frequency f0 of the ICs and several 10x harmonics of f0
• Resonances cause significantly higher impedances!
 If one or more harmonics of f0 coincide with a plane’s resonance frequency, the IC’s
function may fail!
f0
Local dependency of Plane Impedance
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9. When Integrated Circuits Switch ….
TTL Inverter VCC
R1 R2
Q1
Q4 Q
3 D1
V(t)
Q
2
+
- Last
R3
GND
Input Intern Output
• They need charge. 1.8V
• Voltage has to be delivered (for reaching logic levels). VH
• A switching current will occur! VL
GND
Relation between voltage & current?  Ohm’s law
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10. Power Integrity in Reality
Proper Power Supply of a Large FPGA
A Xilinx FPGA with 456 pins:
• Controls a video grabber card
• 64 bits can switch in parallel (worst case, with
a rise time of 750ps)
• Output pin drives into a load of 15pf
The maximum switching current can be
determined by:
Vcc 2.5V
I  n * C *  64 *15 pf  3.2 A
t 0.75ns
Based on this maximum current, the
impedance limit to guarantee a ripple of
less than 125 mV (5% of 2.5 V) :
U 125mV
Z   0.039
I 3.2 A
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11. Power Integrity: Switching Current
• IC Switching current depends on:
- Number of active outputs
- Activity state
- Driver rise and fall times
TTL Inverter VCC
- Clock frequencies
- Load conditions R1 R2
Q1
Q4 Q
3 D1
V(t)
Q
2
+
- Last
R3
GND
Input Intern Output
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12. Example: Ztarget of a Freescale Power-PC
Area to be determined by PCB design
Picture © Freescale
Table © Freescale
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13. PCB Design Process Changing
Traditional design flow to address power integrity issues
Conceptual Test
Schematic Placement Layout Prototyping
Design Measurements
Design flow with power integrity analysis during layout
Concurrent PI Simulation
Conceptual Test
Schematic Placement Layout Prototyping
Design Measurements
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14. Common Management of Power Integrity
Decoupling Capacitors (DeCaps):
• Often used on “per default” basis (eg.; each IC)
• Values are based on past experience or design guidelines (eg.; 47nF, 100nF,…)
• Decision drivers are typically “rules of thumb” or “fear-decouplers”
• Connection between ICs and power-planes using discrete components and long traces
usually result in:
– Parasitic inductances
– Parallel connection in series to GND  very high impedance and parallel capacitor circuit
– Outcome:
‒ Efficiency is reduced (can be narrowed down to zero)
‒ Low-pass filters with low resonance frequencies (LC-Resonance)
‒ Current loops  EMC antennas
Vdd
Ground
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15. Parasitic Inductance of DeCaps
The following inductance should be taken into account for PI consideration:
• Connecting traces (rule of thumb: ~1nH per mm)
• ESL of the DeCap (Package)
• Inductance of the PDS (eg,; Vcc/GND)
• 2 x Via-Inductance, which can be calculated by hand as follows:
With:
  4h  
LVia  2h ln    1 h = PCB-thickness resp. Via-length
 d  
and:
d = Via-diameter
IC Decap
Vcc
GND
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Source: Johnson & Graham’s : A Handbook of Black Magic © Zuken

16. Real Capacitors
Equivalent Circuit
C L ESR
Capacitor
Z
Resonance frequency of a
capacitor
fres  1 / 2 L  C
ESR
fres1 fres2 log f
C=10nF, L= 25nH (including trace)  f res  10 MHz
C=10nF, L= 2.5nH (SMD-Pads)  f res  33 MHz
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17. Decoupling Capacitors and Resonances
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18. Decoupling Capacitors: Design Rules
Distance of decoupling capacitor to IC pin:
- Investigation of the influence of distance d between IC (source) and a
decoupling capacitor
DeCap
d
Source
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19. Decoupling Capacitors: Design Rules
Distance of DeCaps to IC Pin:
 Distance d has significant influence on efficiency and resonance behavior, but not in the
high frequency range (where DeCaps are not effective at all).
Pure Plane
d=2mm
d=5cm
d=10cm
d
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20. Decoupling Capacitors: Design Rules
• Does more DeCaps result in improved resonance behavior?
- Distance = 2cm, up to 4 DeCaps at 10nF
Port2
DeCaps
Source
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21. Decoupling Capacitors: Design Rules
• Variation of the number of the DeCaps
– Identical DeCaps with identical connection
• Consequence: Number of DeCaps have limited impact in quality and
quantity (resonance in frequency point and magnitude) but there is no
general rule  more does not always mean better
Pure Plane
1 Decap
2 Decaps
3 Decaps
4 Decaps
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22. Application: Decoupling Analysis & What If
DeCap potentially not effective ?
Change Value within Lightning from 470p to 100N  Quick What-If
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23. Application: Effectiveness of Decoupling
• Impedance distribution at target
frequencies show impact of
decoupling capacitors
• Indicate quality of placement
location, value and connection
inductance
• Placement or connection can be
changed on the fly in Lightning
for what if capabilities
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24. Application: DDR2 Power Supply
Symetrical modules, with different Power/GND connection
35Ohm @550MHz
D1
V1 D1 D2
11Ohm @650MHz
V1
V2 D2
V2
better
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25. Application: Plate Capacitance of PDS
Plate capacitance should be considered for
power and ground plane overlaps
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26. Application: Decoupling Capacitor
Connection  Inductance Effect
• Automotive Motor Control Unit
– Changed connection strategy reduces inductance from
16nH to 7.5nH
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27. Application: Changing PWR/GND Shapes
to Improve PDN Behavior
Motor Control Unit
– Increased PDS shapes and better connection of decoupling capacitors allows reduction in the
number of decoupling capacitors by 40%  saving PCB and manufacturing costs.
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28. Power Integrity in Reality:
2.5 V PDS Impedance for the Xilinx Spartan3
Target impedance: 0.039
Ohm (=limit voltage ripple
to +/- 5 %)
 Computation time to
get these figures?
Minimum at
66 MHz – intended,
or at least known?
Resonances at 33MhZ and 990 MHz  a problem?
Is a modification of the decoupling scheme or a shift of these
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resonances needed?
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29. There are more voltages to supply…
12 Layer Design  Task: Optimization of PDS Capacitance between the layer
+2.5V
+ 2.5 V and GND 0.47 nF
Capacitance between the layer + 1.2 V and GND 0.48 nF
+1.2V
Impact of Decaps
Impact of Decaps
plane area
plane area
decaps
decaps
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30. Results: Different Power Trace Length
28 mm 28 mm 165 mm
28 mm
86 mm
35 mm
35 mm
25 mm
35 mm
track
plane
plane plane
track
track
30 Length 25 mm Length 86 mm Length 165 mm
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31. DC Case:
+1.8V-GND on Virtex5 Design – DC Voltages
Voltage Distribution
Max. Voltage Drop: 32mV
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32. Summary
Power integrity analysis early in the design flow can save cost and
improve quality
• Early detection of issues in power distribution systems
• Verify effectiveness of decoupling capacitors
• Confirm quality of voltage and current distribution to avoid voltage
drops
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33. The Partner for Success
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