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Analog vlsi

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Khuong Lamborghini
Khuong Lamborghini
TecnologíaEmpresariales
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Analog VLSI Design Nguyen Cao Qui
Introduction to the course ,[object Object],[object Object],[object Object],[object Object],[object Object]
Introduction to the course ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Introduction to the course ,[object Object],[object Object],[object Object],C onversion 10 ‘ Scale ABCB 0.0 F 4.0 D 4.5 D+ 5.0 C 6.0 C+ 7.0 B 7.8 B+ 8.5 A
CONTENTS ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Chapter 1 Introduction to CMOS Design ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Introduction to CMOS Design ,[object Object]
 
The CMOS IC Design Process ,[object Object],[object Object],[object Object],[object Object]
 
 
 
2. CMOS Background ,[object Object],[object Object],NMOS PMOS
2. CMOS Background ,[object Object]
2. CMOS Background ,[object Object],[object Object],[object Object],[object Object],95% of ICs are fabricated in CMOS
3. Technology Scale Down ,[object Object]
3. Technology Scale Down
Chapter 2: The Well ,[object Object],[object Object],[object Object],[object Object]
Chapter 2: The Well ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Chapter 2: The Well ,[object Object]
Chapter 2: The Well ,[object Object]
2.1 Patterning ,[object Object]
2.1 Patterning
2.1 Patterning
2.1.1 Patterning the N-well
2.2 Laying Out the N-well
2.2.1 Design Rules for the N-well
2.3 Resistance Calculation
2.3 Resistance Calculation
2.3 Resistance Calculation ,[object Object]
2.4. PN Junction Physics - Capacitance
2.4. PN Junction Physics - Capacitance
2.5. Design Rules for the Well
Chapter 3: The Metal Layers ,[object Object],[object Object],[object Object]
3.1 The Bonding Pad ,[object Object]
3.1.1 Laying Out the Pad
Capacitance of Metal-to-Substrate
Insulator - Overglass layer
3.2 Design and Layout Using the Metal Layers ,[object Object]
An Example Layout
3.2.2 Parasitics Associated with the Metal Layers
Intrinsic Propagation Delay ,[object Object],The delay of the metal line Where
3.2.3 Design Rules for the Metal Layers
A Layout Trick for the Metal Layers
3.2.4 Contact Resistance
3.4 Layout Examples
3.4 Layout Examples
3.4 Layout Examples
3.4 Layout Examples
3.4 Layout Examples
Chapter 4: The Active and Poly Layers ,[object Object],[object Object],[object Object],[object Object]
Chapter 4: The Active and Poly Layers ,[object Object],[object Object],[object Object],[object Object]
4.1 Layout using the Active and Poly Layers ,[object Object]
The P- and N-Select Layers
The P- and N-Select Layers
The Poly Layer ,[object Object],[object Object],[object Object]
Layout and cross-sectional views of a MOSFET.
Layout and cross-sectional views of a MOSFET.
Layout and cross-sectional views of a MOSFET.
The Poly Wire ,[object Object],[object Object],[object Object],[object Object],[object Object]
The Poly Wire
4.1.1 Process Flow
4.1.1 Process Flow
4.2 Connecting Wires to Poly and Active
4.2 Connecting Wires to Poly and Active
Connecting the P-Substrate to Ground
Layout of an N-Well Resistor
Layout of an NMOS Device
Layout of a PMOS Device
Design Rules
Design Rules
 

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  1. Voltage References