1. By …………..
Ssh –X anukulece@192.168.1.3
Anukul123

2. .v to .vg and .sdc (Digital design
flow)
 Go to the folder having .v file and
fsa0m_a_generic_core_tt1p8v25c.lib
 rc -gui
 read_hdl gggg.v(pit bull)
 set_attribute library fsa0m_a_generic_core_tt1p8v25c.lib
//setting the attribute from generic core having typical value
temperature 25 degree c
 elaborate //it extracted your design over the -gui
 define_clock –p 2000 –name clk [ find /des* -port
ports_in/clk]
//definition of the clock of design
N.I.T Jalandhar, VLSI LAB. Dpt. of ECE 2

3. Synthesize –to _mapped
 report timing
 report power
 write_hdl > gggg_net_list.vg
 write_sdc > gggg_sdc.sdc
N.I.T Jalandhar, VLSI LAB. Dpt. of ECE 3

4. Some problem during conversion .v
to .vg,.sdc
 In always block if u have two edge trigger then u have
to separate that with ‘or’ in place of ‘,’. Example:
always@(posedge clk,posedge rst) F
always@(posedge clk or posedge rst) T
 Have practice of writing in two line while defining
output variable
Example: output reg out; F
output out;
reg out; T
 Initial command is not synthesizable in cadence.
N.I.T Jalandhar, VLSI LAB. Dpt. of ECE 4

5. Backend(make new folder have the
.vg,.sdc,.lib,and .lef files)
 In .lef file u will find header file , antenna rule file and macro file for appropriate rule
 In Soc encounter type
 encounter
 Common timing library
 fsa0m_a_t33_generic_io_tt1p8v25c.lib
 in design tab import design add generic core
1.header6b55.lef
2. fsa0m_a_generic_core.lef
3. FSA0M_A_GENERIC_CORE_ANT_V55.4.lef
 Design import----advanced--------power--------vdd and ground and save as
gggg.conf(configuration)------select auto design
 Again same as .lef put the .io file
 Floor planning and partioning
 In floor planning ……………………leave boundary core to left
N.I.T Jalandhar, VLSI LAB. Dpt. of ECE 5

6. Power rail…..add strips
Set_to_set distance 50
Placement -----standard cell and blocks …………go to
layout view
After routing connection got modified……….
Analysize timing at each and every step
 Change property by hitting ‘q-key’
 Clock routing
 Put some filler cell
N.I.T Jalandhar, VLSI LAB. Dpt. of ECE 6

7. Lab 6(Analog Design Flow)
 Now time to switch analog mode manually design the
inverter and draw the various characteristic.
 Hit icfb
 Provide library name (inv)And attach existing library to
your cell.ie umc_180nm
 Name the cell of your file(inv_cell)
 Add instance by clicking on left side corresponding symbol
or hit ‘i’ from keyboard……..add the required component
from umc180 library or from basic library.
 In next step go to analog environment and set accordingly.
N.I.T Jalandhar, VLSI LAB. Dpt. of ECE 7

8.  You can go for parametric analysis.
N.I.T Jalandhar, VLSI LAB. Dpt. of ECE 8