5. Slope of VTC
or
inverter gain
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 5
6. Steady-State (Static) Output Voltage Behavior
(oC)
(oC)
Tj = Ta + ΘP
Θ -> Thermal Resistance (oC/W)
P → Pstatic, Pdynamic (W)
Pstatic = VDD ID
V DD
P static= [ I D V in =V OL I D V in =V OH ]
2
Minimum area nMOS, pMOS transistor layouts limited by design rules
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 6
16. VDD
0 VDD
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 VT0n 16
17. Take Limit as knRL -> ∞
-> VT0n
-> VT0n
-> VT0n
-> 0
Vout
VDD
knRL -> ∞
semi-ideal VTC
Vin
0 VT0n VDD
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 17
18. 1
V DD
P static average= [ I D V in =V OL I D V in =V OH ]
2
P(Vin = “0”) = 0
Vout = VOL
ID(Vin = “1”) = IL =
Pstatic (average)
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 18
19. Multiplying by RL
W 30 x 10−6 DD −V OL
2V W 25−0.2
5−0.2= 2V −V R L [25−10.2−0.2 25−10.2−0.22
R L= ' = 2
2 −6 ]
L k n 2 DD LT0nV OL −V OL 30 x 10
W
R L=2.05 x 105 NO UNIQUE W/L, RL
L
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 19
20. W 5
R L =2.05 x 10
L
Pstatic (average) [mW]
V DD V DD −V OL
P static average =
2 RL
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 20
21. VOL = 0.147 V or 8.503 V ?
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 21
26. => VGSp = Vin - VDD
=> VDSp = Vout - VDD
IDn = IDp
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 26
27. “Visual” Representation of the CMOS Inverter
A
Vout Vout = Vin - VT0p
A E
-1 Vout = Vin - VT0n
LIN LIN E
SAT
&
OFF
SAT
LIN
LIN
&
-VT0p OFF
-1
Vin
VT0n V th V DD
-VT0n V IL V IH VDD+VT0p
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 27
28. “Visual” Representation of the CMOS Inverter
Vout Vout = Vin - VT0p
A E
-1 Vout = Vin - VT0n
LIN LIN
&
SAT
SAT
SAT
SAT LIN
&
SAT LIN
-VT0p &
-1 SAT
Vin
VT0n V th V DD
-VT0n V IL V IH VDD+VT0p
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 28
29. IDn = IDp
-1 Vout = Vin - VT0p
Vout = Vin - VT0n
V th−V T0p
V th
V th−V T0n
V out
=∞ (iff λ = 0)
V in
-1
V th V DD
-VT0n
V IL V IH
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 29
30. IDn = IDp = 0
0=
IDn = IDp = 0
=0
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 30
31. IDn = IDp
Eq.(1)
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 31
32. (1)
Eq.(1)
VIL (-1)
' VIL '
k W
n k W p d V out
2V in −V T0n = [2V out −V DD 2V in −V DD −V T0p ]
2 L n 2 L p d V in
d V out (-1)
¿[−2V out −V DD ]
d V in
Eq.(2)
SOLVE Eq. (1) and Eq. (2) for Vout and VIL or use simulation.
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 32
33. IDn = IDp
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 33
34. Eq.(3)
Eq.(4)
SOLVE Eq. (3) and Eq. (4) for Vout and VIH or use simulation.
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 34
35. IDn = IDp
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 35
36. Setting for Vin = Vth and solving for Vth
Eq.(5)
where k 'n W / Lnn W / Ln
k R= ' =
k p W / L p p W / L p
RECALL THAT
n p
Usually Ln = Lp is set to min L:
k 'n W / Ln n W n
k R= ' =
k p W / L p p W p
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 36
37. DESIGN OF CMOS INVERTERS
V th =
V T0n
1
kR
V DD V T0p
Eq.(5)
Eq.(5)
1
1
kR
2 Important design
V DD V T0p −V th
Solving Eq.(5) for kR k R =
V th −V T0n
Eq. for CMOS
inverter VTC.
1
If Vth is set to V th =V th ideal = 2 V DD Vth
ideal
0.5 V DD V T0p 2
k R =
0.5 V DD −V T0n
Symmetric CMOS Inverter
If, also th(ideal) and VT0n = - VT0p = VT0
If V k R symetric =1
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 37
38. Vth vs. 1/kR
1 p W p
=
k R n W n
where Ln = Lp
Vth (volts)
1/kR
V th =
V T0n
1
kR
V DD V T0p
VDD = 5V; VT0n = - VT0p = 1 V
1
1
kR
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 38
39. Symmetric CMOS inverter Vth(ideal) and VT0n = - VT0p = VT0 => k R symetric =1
W / L p ≈2.52 W / Ln
FROM Eq. (1) and Eq. (2)
FROM Eq. (3) and Eq. (4)
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 39
40. DERIVE: for Symmetric CMOS Inverter
Symmetric CMOS inverter: Vth = VDD/2, VT0n = - VT0p = VT0 and kR = 1
Eq.(1)
1
Eq.(2) => V IL =V out − 2 V DD
Substitute V out =V IL 1 V DD , V = V and Sym-Inv Cond. into Eq.(1), i.e.
2 in IL
V 2 −2V IL V T0 V 2
IL T0
1
.=2 V 2 −2V IL V DD 2 V IL V T0 −V IL V DD V 2 −V T0 V DD −V 2 V IL V DD − V 2
IL DD IL
4 DD
3
2 V IL V DD −4 V IL V T0 =−V T0 −V T0 V DD V 2
2
4 DD
3 1 3V DD 2V T0 V DD −2V T0
V IL 2 V DD −4V T0 = V 2 −V T0 V DD −V 2 V IL =
4 DD T0 QED
8 V −2VDD T0
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 40
41. EXAMPLE: Compute the noise margins for a symmetric CMOS
inverter has been designed to achieve Vth = VDD/2, where VDD = 5 V
and VT0n = - VT0p = 1 V.
V DD
5 2 3 2
NM H =V OH −V IH =V DD − V DD − V T0 = V DD V T0
8 8 8 8
0 3 2 3 2
NM L =V IL −V OL =V IL = V DD V T0 = V DD V T0
8 8 8 8
RECALL
1. NMH, NML > VDD/2 = 1.25 V
2. Ideal NM => NMH = NML = 2.5 V > VDD/2
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 41
42. Pstatic
Pstatic = 0
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 42
43. If the inverter cell is part of a
standard cell library, it will adhere Smaller Area
to the cell layout protocols. Layout
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 43
44. VDD ≥ Vout > - VT0p
Pstatic > 0
Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 44