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                                   Session 4


Prepared by
          Alaa Salah Shehata
          Mahmoud A. M. Abd El Latif
          Mohamed Mohamed Tala’t
          Mohamed Salah Mahmoud

                                                     Version 02 – October 2011
                                                  Copyright 2006 – Biz/ed
http://www.bized.co.uk




                                              4
           -Data Operators
                  -Aggregate
Contents          -Concatenation
                  -Attributes

           -LABs
                   -Counters
                   -Rotating LEDs




                                                  2
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Session 4

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              Data
            Operators




                                   3
                     Copyright 2006 – Biz/ed
Session 4

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Data Operators                      Concatenation



Used to merge two operands together using the concatenation operator (&).
This result is an array in which length is the sum of lengths of both operands.




  C <= A & B                                            A                    B




                                                              C

                                                                                   4
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Shift registers



                   Example
                      19




                                           5
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Session 4

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Data Operators                Concatenation
                                     A7                     A0
 Shift Right Register:

 A <= „0‟ & A(7 downto 1);

                                      0
                                          A7                A1

                                     A7                     A0
 Shift Left Register:

 A <= A(6 downto 0) & „0‟ ;
                                                            0
                                     A6               A0
                                                                 6
                                                  Copyright 2006 – Biz/ed
Session 4

                                                        http://www.bized.co.uk


Data Operators                 Concatenation
                                             A7                      A0
 Shift Right Register:

 A <= A(7) & A(7 downto 1);


                                             A7 A7                   A1
 we use this shifting when we need to keep
 the sign in our vector and not losing it.

                                             A7 A7 A7                A2




                                                                         7
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Session 4

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Rotating registers



                     Example
                        20




                                             8
                               Copyright 2006 – Biz/ed
Session 4

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Data Operators                Concatenation
                                     A7                    A0
 Rotate Right Register:

 A <= A(0)& A(7 downto 1);



                                     A0 A7                 A1

                                     A7                    A0
 Shift Left Register:

 A <= A(6 downto 0) & A(7);


                                     A6              A0 A7
                                                                9
                                                 Copyright 2006 – Biz/ed
Session 4

                                                            http://www.bized.co.uk


Data Operators                   Aggregate
Provides an easy way of assigning objects of composite types

The aggregate assigns values to a selected elements of an array or a record.

Example 20

Signal data_bus : std_logic_vector(15 downto 0);

data_bus <= (15 downto 8 => '0' , others => '1');

                 “0000000011111111”
data_bus <= (1 | 4 | 7 => '1', 2 | 3 => '0', others => 'Z');
                 “ZZZZZZZZ1ZZ1001Z”
data_bus <= (others => ‘Z');       -- fill data_bus with ones

                 “ZZZZZZZZZZZZZZZZ”

                                                                             10
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            Exercise
               5




                                    11
                       Copyright 2006 – Biz/ed
Session 4

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Write the statement

“0000000100000000”       --16bit



“11111111”               --8 bits



“11110011”               --8bits




                                                    12
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Session 4

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Write the statement

“0000000100000000”       --16bit

        data_bus <= ( 8 => ‘1’ , others => ‘0’   ) ;

“11111111”               --8 bits

        data_bus <= (others => ‘1’ ) ;

“11110011”               --8bits

        data_bus <= ( 3|2 => ‘0’,others => ‘1’ ) ;




                                                                       13
                                                          Copyright 2006 – Biz/ed
Session 4

                                                                           http://www.bized.co.uk



Attributes                                                                 Attribute      Return value
Attributes allow returning information about entities , architectures ,
types , signals                                                            Count’left          0
„left, „right, „high, „length, ‟range, „event, …                           States’left        Idle
                                                                           Word’left           15
Note
Pronounce the apostrophe as “tick “                                       Count’right        127
                                                                          States’right       Write
Example                                                                   Word’right          0


Type count is integer range 0 to 127 ;                                    Count’high         127
                                                                          States’high        Write
Type states is ( idle , decision , read , write ) ;
                                                                          Word’high           15
Type word is array ( 15 downto 0 ) of std_logic ;
                                                                           Count’low           0
Note
                                                                           States’low         Idle
As we know if we need to ask about the rising edge of the clk we           Word’low            0
can say
 if rising_sdge(clk) then                                                 Count’length        128
                                                                          States’length        4
by using attributes we also can ask about the clk with other formula      Word’length         16
that says
if (clk’event and clk = ‘1’) then

                                                                                             14
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• General example on Attributes




                                  Example
                                     21




                                                         15
                                            Copyright 2006 – Biz/ed
Session 4

                                                            http://www.bized.co.uk

ARCHITECTURE examp OF attrs IS
  Type myInt is range 0 to 15;    Type states is (red, yellow, green);
  Type word is array (15 downto 0) of std_logic;
  Signal count: integer;     signal mySig: myInt;
  signal state : states;
BEGIN
  process
    begin
       mySig <= myInt'left; count <= word'left; state <= states'left;
       wait for 10 ns;
       mySig <= myInt'right; count <= word'right; state <= states'right;
       wait for 10 ns;
       mySig <= myInt'low; count <= word'low; state <= states'low;
       wait for 10 ns;
       mySig <= myInt'high; count <= word'high; state <= states'high;
       wait for 10 ns;
       count <= word'length;
       wait;
   end process;
END ARCHITECTURE examp;




                                                                             16
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Sequential Circuits on Modelsim


                                         17
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As clock is found in your design..
the output registered (saved) and appeared next clk cycle
                                                         18
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• 4-Bit binary Counter




                         lab
                          5




                                               19
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• 4-Bit binary Counter with asynchronous load




                                                lab
                                                 6




                                                                      20
                                                         Copyright 2006 – Biz/ed
Session 4

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Assignment
                                  Session-4
4-Bit binary Up-Down Counter with asynchronous load




                                                                      21
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Session 4

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• One way rotating LEDs




                          lab
                           7




                                                22
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Session 4

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Assignment
                         Session-4
Two Ways Rotating LEDs




                                                     23
                                        Copyright 2006 – Biz/ed
Session 4

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Download Session 4 material



        Session 4.pdf

        Labs4.txt




Ask for the material through mail
          start.courses@gmail.com

Facebook group
       start.group@groups.facebook.com



                                                         24
                                            Copyright 2006 – Biz/ed
Session 4

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Questions
                 Session-4




                                             25
                                Copyright 2006 – Biz/ed
Session 4

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Take Your Notes
              Print the slides and take your notes here

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                                                                                                           Copyright 2006 – Biz/ed
Session 4

                                                                                                      http://www.bized.co.uk

Take Your Notes
              Print the slides and take your notes here

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                                                                                                                              27
                                                                                                           Copyright 2006 – Biz/ed
Session 4

                       http://www.bized.co.uk




See You Next Session




                                       28
                          Copyright 2006 – Biz/ed

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Session four

  • 1. http://www.bized.co.uk Session 4 Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud Version 02 – October 2011 Copyright 2006 – Biz/ed
  • 2. http://www.bized.co.uk 4 -Data Operators -Aggregate Contents -Concatenation -Attributes -LABs -Counters -Rotating LEDs 2 Copyright 2006 – Biz/ed
  • 3. Session 4 http://www.bized.co.uk Data Operators 3 Copyright 2006 – Biz/ed
  • 4. Session 4 http://www.bized.co.uk Data Operators Concatenation Used to merge two operands together using the concatenation operator (&). This result is an array in which length is the sum of lengths of both operands. C <= A & B A B C 4 Copyright 2006 – Biz/ed
  • 5. Session 4 http://www.bized.co.uk Shift registers Example 19 5 Copyright 2006 – Biz/ed
  • 6. Session 4 http://www.bized.co.uk Data Operators Concatenation A7 A0 Shift Right Register: A <= „0‟ & A(7 downto 1); 0 A7 A1 A7 A0 Shift Left Register: A <= A(6 downto 0) & „0‟ ; 0 A6 A0 6 Copyright 2006 – Biz/ed
  • 7. Session 4 http://www.bized.co.uk Data Operators Concatenation A7 A0 Shift Right Register: A <= A(7) & A(7 downto 1); A7 A7 A1 we use this shifting when we need to keep the sign in our vector and not losing it. A7 A7 A7 A2 7 Copyright 2006 – Biz/ed
  • 8. Session 4 http://www.bized.co.uk Rotating registers Example 20 8 Copyright 2006 – Biz/ed
  • 9. Session 4 http://www.bized.co.uk Data Operators Concatenation A7 A0 Rotate Right Register: A <= A(0)& A(7 downto 1); A0 A7 A1 A7 A0 Shift Left Register: A <= A(6 downto 0) & A(7); A6 A0 A7 9 Copyright 2006 – Biz/ed
  • 10. Session 4 http://www.bized.co.uk Data Operators Aggregate Provides an easy way of assigning objects of composite types The aggregate assigns values to a selected elements of an array or a record. Example 20 Signal data_bus : std_logic_vector(15 downto 0); data_bus <= (15 downto 8 => '0' , others => '1'); “0000000011111111” data_bus <= (1 | 4 | 7 => '1', 2 | 3 => '0', others => 'Z'); “ZZZZZZZZ1ZZ1001Z” data_bus <= (others => ‘Z'); -- fill data_bus with ones “ZZZZZZZZZZZZZZZZ” 10 Copyright 2006 – Biz/ed
  • 11. Session 4 http://www.bized.co.uk Exercise 5 11 Copyright 2006 – Biz/ed
  • 12. Session 4 http://www.bized.co.uk Write the statement “0000000100000000” --16bit “11111111” --8 bits “11110011” --8bits 12 Copyright 2006 – Biz/ed
  • 13. Session 4 http://www.bized.co.uk Write the statement “0000000100000000” --16bit data_bus <= ( 8 => ‘1’ , others => ‘0’ ) ; “11111111” --8 bits data_bus <= (others => ‘1’ ) ; “11110011” --8bits data_bus <= ( 3|2 => ‘0’,others => ‘1’ ) ; 13 Copyright 2006 – Biz/ed
  • 14. Session 4 http://www.bized.co.uk Attributes Attribute Return value Attributes allow returning information about entities , architectures , types , signals Count’left 0 „left, „right, „high, „length, ‟range, „event, … States’left Idle Word’left 15 Note Pronounce the apostrophe as “tick “ Count’right 127 States’right Write Example Word’right 0 Type count is integer range 0 to 127 ; Count’high 127 States’high Write Type states is ( idle , decision , read , write ) ; Word’high 15 Type word is array ( 15 downto 0 ) of std_logic ; Count’low 0 Note States’low Idle As we know if we need to ask about the rising edge of the clk we Word’low 0 can say if rising_sdge(clk) then Count’length 128 States’length 4 by using attributes we also can ask about the clk with other formula Word’length 16 that says if (clk’event and clk = ‘1’) then 14 Copyright 2006 – Biz/ed
  • 15. Session 4 http://www.bized.co.uk • General example on Attributes Example 21 15 Copyright 2006 – Biz/ed
  • 16. Session 4 http://www.bized.co.uk ARCHITECTURE examp OF attrs IS Type myInt is range 0 to 15; Type states is (red, yellow, green); Type word is array (15 downto 0) of std_logic; Signal count: integer; signal mySig: myInt; signal state : states; BEGIN process begin mySig <= myInt'left; count <= word'left; state <= states'left; wait for 10 ns; mySig <= myInt'right; count <= word'right; state <= states'right; wait for 10 ns; mySig <= myInt'low; count <= word'low; state <= states'low; wait for 10 ns; mySig <= myInt'high; count <= word'high; state <= states'high; wait for 10 ns; count <= word'length; wait; end process; END ARCHITECTURE examp; 16 Copyright 2006 – Biz/ed
  • 17. Session 4 http://www.bized.co.uk Sequential Circuits on Modelsim 17 Copyright 2006 – Biz/ed
  • 18. Session 4 http://www.bized.co.uk As clock is found in your design.. the output registered (saved) and appeared next clk cycle 18 Copyright 2006 – Biz/ed
  • 19. Session 4 http://www.bized.co.uk • 4-Bit binary Counter lab 5 19 Copyright 2006 – Biz/ed
  • 20. Session 4 http://www.bized.co.uk • 4-Bit binary Counter with asynchronous load lab 6 20 Copyright 2006 – Biz/ed
  • 21. Session 4 http://www.bized.co.uk Assignment Session-4 4-Bit binary Up-Down Counter with asynchronous load 21 Copyright 2006 – Biz/ed
  • 22. Session 4 http://www.bized.co.uk • One way rotating LEDs lab 7 22 Copyright 2006 – Biz/ed
  • 23. Session 4 http://www.bized.co.uk Assignment Session-4 Two Ways Rotating LEDs 23 Copyright 2006 – Biz/ed
  • 24. Session 4 http://www.bized.co.uk Download Session 4 material Session 4.pdf Labs4.txt Ask for the material through mail start.courses@gmail.com Facebook group start.group@groups.facebook.com 24 Copyright 2006 – Biz/ed
  • 25. Session 4 http://www.bized.co.uk Questions Session-4 25 Copyright 2006 – Biz/ed
  • 26. Session 4 http://www.bized.co.uk Take Your Notes Print the slides and take your notes here --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- 26 Copyright 2006 – Biz/ed
  • 27. Session 4 http://www.bized.co.uk Take Your Notes Print the slides and take your notes here --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------- 27 Copyright 2006 – Biz/ed
  • 28. Session 4 http://www.bized.co.uk See You Next Session 28 Copyright 2006 – Biz/ed