The document discusses the simulation of a Triple Data Encryption Standard (Triple DES) circuit using VHDL. It provides background on Triple DES, describes the design and structure of the Triple DES circuit in VHDL, and presents the results of testing the encryption and decryption functions of the circuit through simulation. Testing showed the circuit correctly performed encryption and decryption on input data using the Triple DES algorithm. The design utilized some FPGA resources but would require a clock generator and RAM for implementation on an actual FPGA board.

1. Simulation on Triple Data Encryption standard Adviser Aj. Jarern Vongshumyen By Chatsiri Rattana 47221163 Woranart Hasawayukul 47221858

3. Introduction

6. Tools for Development Xilinx Inc.Webpack 8.2i. ModelSim

7. Theory on Triple DES

10. Step 1: Create 16 subkeys, each of which is 48-bits long.

11. Step 2: Encode each 64-bit block of data The Feistel ( F ) function

13. 3DES-EDE E D E k 1 k 2 k 1 Plaintext Ciphertext D E D k 1 k 2 k 1 Ciphertext Plaintext

14. Design on Triple DES

15. Schematic On Top Module

17. Structure on DESCIPHERTOP

18. DESCIPHERTOP 1,2,3 KEYSCHEDULE DES

19. KEYSCHEDULE

20. DESTOP

21. BLOCKTOP

22. E_EXPANSION FUCNTION

23. ADDKEY

24. SBOX

25. PBOX

26. ADDLEFT

27. Device Utilization Summary Logic Utilization Used Available Utilization Slices 1398 4656 30 % Slice FF 1140 9312 12% IOB 305 232 131% GCLKs 1 24 4% MAX CLK 77.548MHz

28. Testing and Result on Triple DES

30. Strategy for test Encryption Decryption Text File Text File Data

31. Test Triple DES ( Encryption ) Input Output

32. Test of Triple DES ( Decryption ) Input Output

33. Conclusion