Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...
The Shift to 3D-IC Structures - Manufacturing and Process Control Challenges
1. The Shift to 3D IC Structures -
Manufacturing and
Process Control Challenges
Ehud Tzuri
Chief Marketing Officer
ChipEx-2012, May 2012
External Use
2. 300mmNOR NAND PVD Metal CVD
Single-wafer E-beam New materials:
III-V, Ge
inspection
MORE Processing CVD: hidden films
INFLECTIONS DRAM 8F2 6F2 Atomic precision CMP Deposited
resist
IN
NEXT Bumping Flowable films Advanced
5 YEARS THAN
Wafer-level interconnect
packaging Dry chemical
Advanced patterning
cleans
350nm 250nm 180nm 130nm 90nm 65nm 45nm 32nm 22nm 14nm 10nm
Double Patterning LAST
Deep-UV Laser
Lithography Epi
Cu damascene
15 YEARS
High aspect ratio Etch
Laser-based
processing
Patterning Films Low-k dielectric 450mm
Lamp-based Interface 3D
Hi-K ALD Processing CMP
Sacrificial
films management NAND
DPN SiON gate Advanced Universal ALD
Reflow HPD transistor
2 External Use
4. Complying with Moore’s Law
Maintaining Cost-Performance
Shrink the feature size: ArF Immersion EUV
Increase wafer size: 200mm 300mm 450mm
Build vertically: 2D 3D
4 External Use
5. Where is 3D Architecture Implemented?
3D
Wafer level
Memory Transistor
packaging
V-NAND FinFET TSV
5 External Use
6. Where is 3D Architecture Implemented?
3D
Wafer level
Memory Transistor
packaging
V-NAND FinFET TSV
6 External Use
7. Flash Roadmap*
* The future is coming sooner than we thought
Source: J.Choi, Samsung, The 2nd International Memory Workshop, May.16, 2010
External Use 7
8. From 2D to 3D Flash NAND
Sourceline
Wordlines
Select gate
A folded, vertically stacked NAND string
Cells are generated inside a high-aspect-ratio (HAR) contact hole
Benefits:
– Memory density is less dependent on patterning
– Reduced coupling between memory cells
– Cost scalability
Image Sources:
Left:IMFT 25-nm MLC NAND: technology scaling barriers broken, DONG YI Technology Group, Published Date:2010-3-23
Right: Pipe-shaped BiCS Flash Memory with 16 Stacked Layers…/Ryota Katsumata - 2009 Symposium on VLSI Technology
External Use
9. 3D NAND Process Challenges
TEM Image of 69-Layer Oxide/Nitride Stack
Surface / interface roughness
Top
Film stress control for low wafer bow
Fastest cycle time
Bottom
Excellent stacked particle
performance
Etch profile - ability to open HAR SEM X-section of double etched stack
stacks
Complex multi-stack requires
precise process monitoring –
thickness, RI, etch profile and defects Source:
Pipe-shaped BiCS Flash Memory with 16 Stacked Layers…/Ryota
Katsumata - 2009 Symposium on VLSI Technology
9 External Use
10. 3D NAND Metrology & Inspection Challenges
Imaging of HAR
contact hole
Slit & plate etch
along its depth
inspection &
imaging
Charge Trap Embedded defects:
material thickness Deep in the stack
& uniformity along
contact depth
10 External Use
11. Where is 3D Architecture Implemented?
3D
Wafer level
Memory Transistor
packaging
V-NAND FinFET TSV
11 External Use
12. Planar vs. Trigate (FinFET) Transistor
Benefits
– Gate surrounds Si from 3 directions, thus,
increasing control of over channel
reduced leakage
– Can operate at lower voltage with good
performance, reducing active power by
>50%
Source: Intel 22nm Trigate announcement , 4/19/2011
External Use
13. FinFet – Process Challenges
Spacer Gate Stack (high-k & metal gate)
• Complete spacer removal from fin area • Material selectivity
• Material deposition thickness
uniformity on vertical walls
• Metal gate composition uniformity/stability
Fin
Fin Formation:
• Precision etch
STI
• Structural integrity (collapse, Oxide
erosion, thermal shock)
• Precise Recess to control fin Fin Junctions:
height • Conformal doping
• Channel materials to increase on sidewalls
mobility
13 External Use
14. FinFET – Process Control Challenges
Lg
Measurement of
Lg gate CD across the
Fin height
Lg
Detection & Review of
defects on Fin sidewalls after
gate etch
Measurement of Fin
sidewall angle to
control the 3D
transistor width
14 External Use
15. Transistor Roadmap: Applied Materials View
Planar CMOS FinFET III-V FinFET
New Fin
Gate Material
Fin
STI STI
Oxide
Oxide
No end in sight for Moore’s Law – for the next decade
15 External Use
16. Where is 3D Architecture Implemented?
3D
Wafer level
Memory Transistor
packaging
V-NAND FinFET TSV
16 External Use
17. 3D Integration & TSV
TSV is a process in which wafers are: thinned, stacked & interconnected
All flows include creation of deep holes and filling them with Cu
interconnect
Source: DAC, 2½D Integrated Circuits, Wednesday, January 26, 2011 , Paul McLellan / Source: “Through-Silicon Via (TSV)””, Vol. 97, 0018-9219/$25.00 2009
IEEE No. 1, January 2009 | Proceedings of the IEEE
17 External Use
18. TSV – Process Control Challenges
Ta/TaN/Au CVD-SiO2 Wafer inspection for surface
defects on TSV sidewalls and
bottom
Si substrate
Interlayer
Passivation layer
Bonding pad
Adhesive
Handle wafer
HAR SEM-based defect review for
sidewall and bottom defects;
including over-etch
18 External Use
19. Common Challenges
Defects of importance are located in the 3rd dimension;
they need to be found & imaged
Measurements of the 3rd dimension (HAR, SWA) need to
be performed
Current state of the art M&I tools have limitations to do so
19 External Use
20. Possible Solutions
SEM-based imaging
Optical metrology
X-ray
Destructive technologies
20 External Use
21. Possible Solutions – The Leading Candidate
SEM-based imaging
3D imaging E-beam inspection
techniques with SEM (Voltage Contrast)
(Resolution)
21 External Use
22. Summary
The future is here… 3D transistors and TSV are already a
reality, VNAND is just around the corner
3D Key challenges are related (mainly) to process
integration and process control
Traditional process control solutions might not be sufficient
E-Beam based techniques have the potential to become the
process control enablers
22 External Use