Snug2007 Presentation

System Level Verification - A case analysis with Virtio (DesignWare ™ Virtual Platforms) Kal yan Chakravadhanula ASIC Design Engineer Texas Instruments, San Diego Platform Validation Engineer

Purpose ,[object Object],[object Object],[object Object],[object Object]

Outline ,[object Object],[object Object],[object Object],[object Object],[object Object]

Introduction ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Where do we fit? ,[object Object],[object Object],[object Object],[object Object],Software team Hardware team

OMAPV2230 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],DesignWare ™ Virtual Platforms Background

DesignWare ™ Virtual Platforms Background Board-level System IO Mem Simulation Infrastructure Fast Instruction-set Simulators Transaction-level Interfaces High-speed C++ Models Graphical Magic-C FSM Models User Interface Emulation Virtual I/O System-on-Chip Func Peripherals Virtual I/O & User Interface CPU Instruction -accurate ISS Func TLM Bus Func TLM Bus

DesignWare ™ Virtual Platforms Compelling Features ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

DesignWare ™ Virtual Platforms VPOM-V2230 Virtual Platform VPOM-V2230 (Virtual Platform) Cockpit (Virtual Platform) Code Composer Studio (Multi-core Debugger)

DesignWare ™ Virtual Platforms Software Development Tasks ,[object Object],[object Object],[object Object],[object Object],[object Object]

DesignWare ™ Virtual Platforms Benefits ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

DesignWare ™ Virtual Platforms Requirements & Learning Period ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],DesignWare ™ Virtual Platforms Problems & Minor Issues Resolved Resolved

Software Development Flow Chip Design Prototype Silicon Manufacturing Development Board Design Board Mounting time Virtual Platform Development Firmware Develop. Firmware Debug Device Driver Development Firmware Debug Device Driver Development Software Development & Debug Start (traditional approach) Software Development & Debug Start (VP Approach) Time-to-Market Gain

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],DesignWare Virtual Platforms Recommended Improvements

Results ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Acknowledgements ,[object Object],[object Object],[object Object],[object Object]

Snug2007 Presentation

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Snug2007 Presentation