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Seminar


                  Hard IPs

      Shankardas Deepti Bharat
              CGB0911002
                  VSD529
    M.Sc.[Engg.] in VLSI System Design
Module Title: Field Reconfigurable Hardware Systems
       Module Leader: Asst. Prof. Lasitha M




              M. S. Ramaiah School of Advanced Studies   1
Outline


• Semiconductor IPs

• Soft vs. Hard IPs

• List of Hard IP vendors

• ARM Cortex-A9

• PowerPC 405

• MIPS32-4Kc

• Summary

• References




                        M. S. Ramaiah School of Advanced Studies   2
Semiconductor IPs
•   Semiconductor intellectual property (IP) blocks, also known as IP cores, are reusable design

    components that are used to build ICs

•   Main attraction of IP cores is that they accelerate product development and shorten time to
    market

•   Semiconductor IP contracts typically consist of three cost components: one-time front-end
    license fee, support and royalties.
                          Table 1. Semiconductor IPs categories




                                  M. S. Ramaiah School of Advanced Studies                         3
Hard vs. Soft IPs




Figure 1. Hard and Soft IPs

                  M. S. Ramaiah School of Advanced Studies   4
Soft and hard IPs

•   Soft cores are IP blocks that describe the functionality of the IP component.

•   Delivered using high-level hardware description languages derived from computer
    programming languages.

•   The major advantages of soft cores include their customizability and are typically
    independent of the specific manufacturing process used to make the chips.

•   Hard IP cores, in contrast, are closely tailored to the specific manufacturing process used
    to make the chip.

•   Delivered in the form of a mask-level layout.

•   The main benefit of hard IP cores is that they can be pre-tested in a specific
    manufacturing process. This typically means faster time-to-market with less risk and
    less development cost.

•   As a hard IP core is optimized for a specific manufacturing process, it is, however,
    usually impossible for the end-users to modify or configure hard IP cores.



                                M. S. Ramaiah School of Advanced Studies                          5
List of Hard IPs vendors

•   ARM Ltd - ARM

•   Freescale - ColdFire

•   IBM - PowerPC

•   Intel - x86 Atom

•   MIPS Technologies - MIPS

•   Sun Microsystems - OpenSPARC

•   Tensilica - Xtensa

•   Digital Core Design - 8051, 80251, 68000

•   Dolphin Integration - 8051, 80251

•   EnSilica - eSi-RISC




                            M. S. Ramaiah School of Advanced Studies   6
ARM (Advanced RISC Machine)


•   Founded in 1990, headquartered at UK.

•   Characteristic feature of ARM processors is their low electric power consumption,
    which makes them particularly suitable for use in portable devices

•   ARM processors are used as the main CPU for most mobile phones

•   Unlike other microprocessor corporations, ARM only licenses its technology as
    intellectual property (IP), rather than manufacturing its own CPUs.

•   Intel, Samsung, Texas Instruments, Freescale , Nvidia , Qualcomm and Renesas have all
    licensed ARM technology.

•   In 2010, over 6.1 billion ARM-based chips were sold making it the world's leading
    semiconductor intellectual property (IP) supplier.




                               M. S. Ramaiah School of Advanced Studies                     7
Design characteristics of Cortex A9




       Table 2. Speed vs. Power optimized macro




         M. S. Ramaiah School of Advanced Studies   8
ARM Processors




Figure 2. Overview of ARM processors                      Figure 3. Current Cortex A9 adoption


                            M. S. Ramaiah School of Advanced Studies                             9
ARM Cortex A9 floor plan and configuration




Figure 4. Floor plan of Cortex A9
                              M. S. Ramaiah School of Advanced Studies   10
ARM Cortex A9 architecture




        Figure 5. Cortex A9 architecture

     M. S. Ramaiah School of Advanced Studies   11
Explanation of Individual blocks

PL310 L2 Cache Controller ensures high data throughput and maximum performance

•   Support for multiple outstanding AXI transactions on each interface

•   Support for parity and ECC RAMS

•   Support for synchronous half clock ratios to reduce latencies on high speed processor
    designs

•   Auto preload on instruction miss

Floating Point Unit – Delivers single and double precision FPU for accelerated 2D/3D,
    imaging and scientific computation

Program Trace Unit – PTU is a real-time trace module providing instruction tracing of a
    processor. Similar to single stepping in microprocessors. The program flow trace
    architecture provides full information about exceptions, and the instruction set state,
    security state, and current Context ID of the processor. It can also provide cycle count
    information, and time stamping.


                                 M. S. Ramaiah School of Advanced Studies                      12
…Continued

Bus Interface Unit

•   Increased tolerance to memory latencies

•   Up to 16 outstanding bus transactions per processor

•   Out of order execution enabling execution of more than 30 instructions

•   Multicore L1 cache-to-cache transfer capabilities reducing system power

NEON Media Processing Engine

•   Accelerating media and signal processing functions for increased application specific
    performance with the convenience of consolidated application software development
    and support




                               M. S. Ramaiah School of Advanced Studies                     13
ARM Operating modes

                             Seven basic operating modes exist:
                                   1.    User: Unprivileged mode under which most
                                         tasks run
                                   2.    FIQ: Entered when a high priority interrupt is
                                         raised
                                   3.    IRQ: Entered when a low priority interrupt is
                                         raised
                                   4.    Supervisory: Entered on reset and when a
                                         software Interrupt instruction is executed
                                   5.    Abort: Used to handle memory access
                                         violations
                                   6.    Undefined: Used to handle undefined
                                         instructions
                                   7.    System: Privileged mode using the same
                                         registers as user mode.
Figure 6. Operating modes
                            M. S. Ramaiah School of Advanced Studies                      14
POWER PC 405




Figure 7. PowerPC 405 architecture

    M. S. Ramaiah School of Advanced Studies   15
POWER PC 405 Specs

Specifications
• Technology: 0.25 µm CMOS process
• Frequency: 0-200MHz
• Performance: 228 Dhrystone 2.1 MIPS @ 200MHz (est.)
• Supply voltage: 2.5V
• Die Size: 2.0mm² for CPU only
• Power (typ.): 400mW @ 200MHz, CPU only
Features
• 32 bit architecture
• Flexible memory management.
• MAC instructions for computationally intensive application.
• Enhance debug capability.
• Cache memory- 16 kb , set associative mapping.
• Five stage of pipelining with single cycle executive.



                        M. S. Ramaiah School of Advanced Studies   16
MIPS

The MIPS32® M4K® Hard IP Cores are technology-specific implementations of the
synthesizable 32-bit MIPS32 M4K core.

• Available implementations include area optimized and performance optimized cores
    targeting SMIC 0.18µm.

•   Chip developers or system OEMs who are building complex SoC ASIC devices can
    significantly reduce design time, resources, and time to-market by using M4K Hard IP
    Cores.

• Target markets for these cores include Microcontrollers, Automotive, Cell phones
• Based on MIPS32 architecture for high performance
• Extensive clock gating reduces power consumption without reducing application
    performance
• Enhanced JTAG (EJTAG) debug with trace and fast download enable quick and easy
    debugging



                             M. S. Ramaiah School of Advanced Studies                      17
…Continued

• All major operating systems and compiler tool chains, and hundreds of third-party
  development tools, support the MIPS architecture
• Testability features include BIST and full scan
• Supports CorExtend capability which enables users to significantly enhance the value and
  competitive advantage of their SoC products


                         Table 3 MIPS 32-bit MIPS M4K cores

                           0.18µm SMIC – Speed 0.18µm SMIC - Area
             Process
                                   Opt                Opt

           Frequency               138 MHz                      105 MHz
            Core Size            0.65 sq. mm                  0.38 sq. mm




                              M. S. Ramaiah School of Advanced Studies                       18
Features of M4K IP core

Hard Microprocessor Cores
• 110 MHz in .18µm SMIC process – Area optimized
• 137 MHz in .18µm SMIC process - Speed optimized
32-bit MIPS32 enhanced architecture
• 32-bit address and data paths
• Bit field instructions
• Vectored interrupts
Memory-management unit
• Simple Fixed Mapping Translation mechanism
Power control
• Power-down mode (triggered by WAIT instruction)
• Support for extensive use of local gated clocks
EJTAG debug
• Support for single stepping
• Virtual instruction and data address breakpoints
                        M. S. Ramaiah School of Advanced Studies   19
Summary
                         Table 4 MIPS Vs Power PC Vs Cortex A9
      Parameter            MIPS M4K IP              Power 405 IP           ARM Cortex A9
        Process            0.18µm SMIC –           0.25 µm CMOS             40nm TSMC
                              Speed Opt                process
         Cores                      1                      1                       2
       Frequency               138 MHz                 200MHz                 800MHz
       Core Size               0.65 mm²                2.0 mm²                 4.6 mm²
    Pipeline stages                 5                      7                       8
       Registers                 32-bit            32-bit (supports             64-bit
                                                    64-bit as well)
        FLOPS             Slower operations       Faster operations            Fastest

Overall the Power PC is a better architecture than the MIPS architecture because it is
capable of handling more instructions, it is able do more operations as far as branching and
floating point operations and it is a more efficient architecture in handling various
complexities in data and memory.


                                M. S. Ramaiah School of Advanced Studies                       20
References

[1]      ARM    (2009)       ‘The   ARM     Cortex-A9     Processors’       [online]   available   at
  <http://www.arm.com/files/pdf/ARMCortexA-9Processors.pdf>Retrieved on 14 Dec 2011

[2]   Rob Rutenbar A., ‘Semiconductor IP for Digital & Analog Designs’ , Carnegie Mellon
  University, Pittsburgh, 2004

[3] Ian Rickards, ‘ARM Architecture & NEON’, Stanford University, Stanford, California, 2010

[4] IBM Microelectronics Division, ‘The Power PC 405 Core’ [White paper] North Carolina,
  1998

[5] MIPS (2005) ‘MIPS32-Kc IP core’ [online] available at <www.mips.com/products/cores/hard-
  ip-cores/> Retrieved on 15 Dec 2011




                                 M. S. Ramaiah School of Advanced Studies                               21
Thank You




M. S. Ramaiah School of Advanced Studies   22

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Hard ips pdf

  • 1. Seminar Hard IPs Shankardas Deepti Bharat CGB0911002 VSD529 M.Sc.[Engg.] in VLSI System Design Module Title: Field Reconfigurable Hardware Systems Module Leader: Asst. Prof. Lasitha M M. S. Ramaiah School of Advanced Studies 1
  • 2. Outline • Semiconductor IPs • Soft vs. Hard IPs • List of Hard IP vendors • ARM Cortex-A9 • PowerPC 405 • MIPS32-4Kc • Summary • References M. S. Ramaiah School of Advanced Studies 2
  • 3. Semiconductor IPs • Semiconductor intellectual property (IP) blocks, also known as IP cores, are reusable design components that are used to build ICs • Main attraction of IP cores is that they accelerate product development and shorten time to market • Semiconductor IP contracts typically consist of three cost components: one-time front-end license fee, support and royalties. Table 1. Semiconductor IPs categories M. S. Ramaiah School of Advanced Studies 3
  • 4. Hard vs. Soft IPs Figure 1. Hard and Soft IPs M. S. Ramaiah School of Advanced Studies 4
  • 5. Soft and hard IPs • Soft cores are IP blocks that describe the functionality of the IP component. • Delivered using high-level hardware description languages derived from computer programming languages. • The major advantages of soft cores include their customizability and are typically independent of the specific manufacturing process used to make the chips. • Hard IP cores, in contrast, are closely tailored to the specific manufacturing process used to make the chip. • Delivered in the form of a mask-level layout. • The main benefit of hard IP cores is that they can be pre-tested in a specific manufacturing process. This typically means faster time-to-market with less risk and less development cost. • As a hard IP core is optimized for a specific manufacturing process, it is, however, usually impossible for the end-users to modify or configure hard IP cores. M. S. Ramaiah School of Advanced Studies 5
  • 6. List of Hard IPs vendors • ARM Ltd - ARM • Freescale - ColdFire • IBM - PowerPC • Intel - x86 Atom • MIPS Technologies - MIPS • Sun Microsystems - OpenSPARC • Tensilica - Xtensa • Digital Core Design - 8051, 80251, 68000 • Dolphin Integration - 8051, 80251 • EnSilica - eSi-RISC M. S. Ramaiah School of Advanced Studies 6
  • 7. ARM (Advanced RISC Machine) • Founded in 1990, headquartered at UK. • Characteristic feature of ARM processors is their low electric power consumption, which makes them particularly suitable for use in portable devices • ARM processors are used as the main CPU for most mobile phones • Unlike other microprocessor corporations, ARM only licenses its technology as intellectual property (IP), rather than manufacturing its own CPUs. • Intel, Samsung, Texas Instruments, Freescale , Nvidia , Qualcomm and Renesas have all licensed ARM technology. • In 2010, over 6.1 billion ARM-based chips were sold making it the world's leading semiconductor intellectual property (IP) supplier. M. S. Ramaiah School of Advanced Studies 7
  • 8. Design characteristics of Cortex A9 Table 2. Speed vs. Power optimized macro M. S. Ramaiah School of Advanced Studies 8
  • 9. ARM Processors Figure 2. Overview of ARM processors Figure 3. Current Cortex A9 adoption M. S. Ramaiah School of Advanced Studies 9
  • 10. ARM Cortex A9 floor plan and configuration Figure 4. Floor plan of Cortex A9 M. S. Ramaiah School of Advanced Studies 10
  • 11. ARM Cortex A9 architecture Figure 5. Cortex A9 architecture M. S. Ramaiah School of Advanced Studies 11
  • 12. Explanation of Individual blocks PL310 L2 Cache Controller ensures high data throughput and maximum performance • Support for multiple outstanding AXI transactions on each interface • Support for parity and ECC RAMS • Support for synchronous half clock ratios to reduce latencies on high speed processor designs • Auto preload on instruction miss Floating Point Unit – Delivers single and double precision FPU for accelerated 2D/3D, imaging and scientific computation Program Trace Unit – PTU is a real-time trace module providing instruction tracing of a processor. Similar to single stepping in microprocessors. The program flow trace architecture provides full information about exceptions, and the instruction set state, security state, and current Context ID of the processor. It can also provide cycle count information, and time stamping. M. S. Ramaiah School of Advanced Studies 12
  • 13. …Continued Bus Interface Unit • Increased tolerance to memory latencies • Up to 16 outstanding bus transactions per processor • Out of order execution enabling execution of more than 30 instructions • Multicore L1 cache-to-cache transfer capabilities reducing system power NEON Media Processing Engine • Accelerating media and signal processing functions for increased application specific performance with the convenience of consolidated application software development and support M. S. Ramaiah School of Advanced Studies 13
  • 14. ARM Operating modes Seven basic operating modes exist: 1. User: Unprivileged mode under which most tasks run 2. FIQ: Entered when a high priority interrupt is raised 3. IRQ: Entered when a low priority interrupt is raised 4. Supervisory: Entered on reset and when a software Interrupt instruction is executed 5. Abort: Used to handle memory access violations 6. Undefined: Used to handle undefined instructions 7. System: Privileged mode using the same registers as user mode. Figure 6. Operating modes M. S. Ramaiah School of Advanced Studies 14
  • 15. POWER PC 405 Figure 7. PowerPC 405 architecture M. S. Ramaiah School of Advanced Studies 15
  • 16. POWER PC 405 Specs Specifications • Technology: 0.25 µm CMOS process • Frequency: 0-200MHz • Performance: 228 Dhrystone 2.1 MIPS @ 200MHz (est.) • Supply voltage: 2.5V • Die Size: 2.0mm² for CPU only • Power (typ.): 400mW @ 200MHz, CPU only Features • 32 bit architecture • Flexible memory management. • MAC instructions for computationally intensive application. • Enhance debug capability. • Cache memory- 16 kb , set associative mapping. • Five stage of pipelining with single cycle executive. M. S. Ramaiah School of Advanced Studies 16
  • 17. MIPS The MIPS32® M4K® Hard IP Cores are technology-specific implementations of the synthesizable 32-bit MIPS32 M4K core. • Available implementations include area optimized and performance optimized cores targeting SMIC 0.18µm. • Chip developers or system OEMs who are building complex SoC ASIC devices can significantly reduce design time, resources, and time to-market by using M4K Hard IP Cores. • Target markets for these cores include Microcontrollers, Automotive, Cell phones • Based on MIPS32 architecture for high performance • Extensive clock gating reduces power consumption without reducing application performance • Enhanced JTAG (EJTAG) debug with trace and fast download enable quick and easy debugging M. S. Ramaiah School of Advanced Studies 17
  • 18. …Continued • All major operating systems and compiler tool chains, and hundreds of third-party development tools, support the MIPS architecture • Testability features include BIST and full scan • Supports CorExtend capability which enables users to significantly enhance the value and competitive advantage of their SoC products Table 3 MIPS 32-bit MIPS M4K cores 0.18µm SMIC – Speed 0.18µm SMIC - Area Process Opt Opt Frequency 138 MHz 105 MHz Core Size 0.65 sq. mm 0.38 sq. mm M. S. Ramaiah School of Advanced Studies 18
  • 19. Features of M4K IP core Hard Microprocessor Cores • 110 MHz in .18µm SMIC process – Area optimized • 137 MHz in .18µm SMIC process - Speed optimized 32-bit MIPS32 enhanced architecture • 32-bit address and data paths • Bit field instructions • Vectored interrupts Memory-management unit • Simple Fixed Mapping Translation mechanism Power control • Power-down mode (triggered by WAIT instruction) • Support for extensive use of local gated clocks EJTAG debug • Support for single stepping • Virtual instruction and data address breakpoints M. S. Ramaiah School of Advanced Studies 19
  • 20. Summary Table 4 MIPS Vs Power PC Vs Cortex A9 Parameter MIPS M4K IP Power 405 IP ARM Cortex A9 Process 0.18µm SMIC – 0.25 µm CMOS 40nm TSMC Speed Opt process Cores 1 1 2 Frequency 138 MHz 200MHz 800MHz Core Size 0.65 mm² 2.0 mm² 4.6 mm² Pipeline stages 5 7 8 Registers 32-bit 32-bit (supports 64-bit 64-bit as well) FLOPS Slower operations Faster operations Fastest Overall the Power PC is a better architecture than the MIPS architecture because it is capable of handling more instructions, it is able do more operations as far as branching and floating point operations and it is a more efficient architecture in handling various complexities in data and memory. M. S. Ramaiah School of Advanced Studies 20
  • 21. References [1] ARM (2009) ‘The ARM Cortex-A9 Processors’ [online] available at <http://www.arm.com/files/pdf/ARMCortexA-9Processors.pdf>Retrieved on 14 Dec 2011 [2] Rob Rutenbar A., ‘Semiconductor IP for Digital & Analog Designs’ , Carnegie Mellon University, Pittsburgh, 2004 [3] Ian Rickards, ‘ARM Architecture & NEON’, Stanford University, Stanford, California, 2010 [4] IBM Microelectronics Division, ‘The Power PC 405 Core’ [White paper] North Carolina, 1998 [5] MIPS (2005) ‘MIPS32-Kc IP core’ [online] available at <www.mips.com/products/cores/hard- ip-cores/> Retrieved on 15 Dec 2011 M. S. Ramaiah School of Advanced Studies 21
  • 22. Thank You M. S. Ramaiah School of Advanced Studies 22