1. IP Re Engineering – Challenges

3. IP Re Use and Challenges

4. IP Re-Engineering Activities

5. Internal IP Vs Third Party IP

6. Challenges and solutions

7. Challenges

8. Internal Vs External Team

9. Capabilities of the external Team

10. Solutions from MindTree

11. IP ReD

12. CSoC Initiative

13. ConclusionSlide 2

14. Introduction IP Reuse Time to Market Cost Optimized area, performance IP Re-engineering Engineering activities that are aimed to customize, port and make the existing IP available for new designs Challenges: Porting to different Technology libraries (Power, Performance) Verification/Validation/Proto type (Quality) Quality Documentation Support for different teams (internal/external) Enablers: Standard processes/methodology/Framework for Reusable IP Development IP Qualification and Verification Chip Integration IP Distribution and support Slide 3

15. IP Re Engineering Activities Design Feature Enhancements, Functionality modifications (fixing bugs) Optimizing the design for Power, Performance, Area Interface/Bus modifications Making the design more DFT/implementation friendly Verification/Validation Verification Environment optimization for coverage improvement Modifications to reflect and test the DUT enhancements Methodology migration (e – SV; Legacy – HVL) Integration/Physical Implementation/Maintenance Validating the IP for Integration Flow validation Release / Version Control User Documentation/update Slide 4

16. Internal IP Vs Third Party IP Internal IP IP that were developed and used within the organization Standard based, proprietary More visibility to the different designs in which the IP was used Access to the design team and details of the design, environment Legacy environment, custom tool flow and proprietary design components Integration issues due to insufficient documentation and validation Support from the IP owner to re-engineer the IP is possible Third Party IP Independent vendor developed IP Mostly Standard based Lesser visibility to the different design scenarios in which the IP was used Better user documentation possible as the IP is to be shared with different users Good qualification process to be in place before the reuse Support for customization from the vendor is key for success Slide 5

17. Challenges and Solutions

19. Resource optimization (activities Vs resources)

20. Legacy and third party IP

22. Multiple SoC Platforms

24. Different flow qualification (CAD)

25. Metrics collection and analysis

26. Benchmarking & Certification

28. Support for global teams and local centers

29. Issue based support

31. Support for existing IP

32. Multiple Target Platforms (Proc, Bus, OS..)Key Challenges

33. Internal Team Vs Design Services Team.. More often the re-engineering or customization tasks are centered around Technology Migration, Bus interface modification Targeting different SoC platforms, resolving integration issues Improving the quality of the IP (Performance, Power, Area) Optimization of the design and verification environment (coverage improvement for functionality, manufacturing etc.,) Engaging a third party team for effective use of the resources and focused IP re engineering will result in Cost savings due to the effective utilization of the team that manages the IP enhancements and improvements Enables the customer team to focus on the domain specific activities Becomes a central team that supports different design teams Serves as a common knowledge platform where the project experiences are fed back and made available for different teams Slide 8

34. Capabilities of the Partner Slide 9

35. IP ReD

36. Slide 11 Design/Verification IP Re-Engineering Life Cycle

38. IP Re-eng schedule and schedule confidence

39. IP Re-eng effort estimate – leading to WBS

40. Clearly defined Customers & MindTree role in re-eng activity, Receivable and Deliverable

41. Quality of deliverables

42. Entry:

43. Customer Requirements

44. Latest Data Base of the IP

45. Standard Specification (Optional)

46. Exit:

47. Approved Feasibility Report - Effort, Scope, Schedule, Current Status

49. Follow the guidelines for different scenarios for re-eng and ensure less execution

50. Different phases of execution - Design change, RTL Modification, Verification, Synthesis, DFT, STA, P&R

51. Each phase is followed by an internal review and tracking

52. Entry:

53. RTL Data Base

54. Feasibility Report and Guidelines

55. Customer Requirement Specification

56. Exit Criteria:

57. Re-Engineered IP Database

59. Supported by a well defined check-list for each activity

60. Check IP Quality and Use version control to track all the releases

61. Systematic bug tracking

62. Reviews and Sign-off at each stage

63. Package into MindTree or Customer format

64. Post delivery support

65. Entry:

66. Modified IP Database

67. Quality check metrics

68. Exit Criteria:

70. Slide 16 Advantages Rapid Prototyping of SoC’s Unified Platform from Architecture Exploration to System Development Architecture Exploration Virtual Prototyping SoC Development & Verification IP / SoC Validation Seamless Software (Low Level Firmware, Middleware, Application) Development GUI based Automation Framework CSoC Uniqueness Seamless Migration from AE, VPP, SoC Development to Prototyping No Processor Dependencies Adaptive Verification Environment

71. Slide 17 Adaptive Verification Environment

72. Slide 18 Validation Prototype

73. Slide 19 Successful Customers Happy People Innovative Solutions Our Mission Rajagopalan_venktesan@mindtree.com www.mindtree.com © 2010 MindTree Limited CONFIDENTIAL: For limited circulation only