3. Contents
1 Introduction ............................................................................................................ 39
1.1 Overview ......................................................................................................... 42
1.2 Intel® ICH7 Family High-Level Component Differences ........................................... 50
2 Signal Description ................................................................................................... 51
2.1 Direct Media Interface (DMI) to Host Controller ..................................................... 55
2.2 PCI Express* (Desktop and Mobile Only) .............................................................. 55
2.3 Platform LAN Connect Interface (Desktop and Mobile Only)..................................... 56
2.4 EEPROM Interface (Desktop and Mobile Only)........................................................ 56
2.5 Firmware Hub Interface (Desktop and Mobile Only)................................................ 56
2.6 PCI Interface .................................................................................................... 57
2.7 Serial ATA Interface (Desktop and Mobile Only) ..................................................... 59
2.8 IDE Interface .................................................................................................... 60
2.9 LPC Interface.................................................................................................... 62
2.10 Interrupt Interface ............................................................................................ 62
2.11 USB Interface ................................................................................................... 63
2.12 Power Management Interface.............................................................................. 64
2.13 Processor Interface............................................................................................ 66
2.14 SMBus Interface................................................................................................ 68
2.15 System Management Interface............................................................................ 68
2.16 Real Time Clock Interface ................................................................................... 69
2.17 Other Clocks..................................................................................................... 69
2.18 Miscellaneous Signals ........................................................................................ 70
2.19 AC ’97/Intel® High Definition Audio Link ............................................................... 71
2.20 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) .................................... 72
2.21 Intel® Quick Resume Technology (Intel® ICH7DH Only) ......................................... 72
2.22 General Purpose I/O Signals ............................................................................... 72
2.23 Power and Ground ............................................................................................. 74
2.24 Pin Straps ........................................................................................................ 76
2.24.1 Functional Straps ................................................................................... 76
2.24.2 External RTC Circuitry ............................................................................. 78
3 Intel® ICH7 Pin States............................................................................................. 79
3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 79
3.2 IDE Integrated Series Termination Resistors.......................................................... 80
3.3 Output and I/O Signals Planes and States............................................................. 81
3.4 Power Planes for Input Signals ............................................................................ 90
4 Intel® ICH7 and System Clock Domains................................................................... 95
5 Functional Description ............................................................................................. 99
5.1 PCI-to-PCI Bridge (D30:F0) ................................................................................ 99
5.1.1 PCI Bus Interface ................................................................................... 99
5.1.2 PCI Bridge As an Initiator ........................................................................ 99
5.1.2.1 Memory Reads and Writes.......................................................... 99
5.1.2.2 I/O Reads and Writes .............................................................. 100
5.1.2.3 Configuration Reads and Writes ................................................ 100
5.1.2.4 Locked Cycles......................................................................... 100
5.1.2.5 Target / Master Aborts ............................................................. 100
5.1.2.6 Secondary Master Latency Timer............................................... 100
5.1.2.7 Dual Address Cycle (DAC) ........................................................ 100
5.1.2.8 Memory and I/O Decode to PCI................................................. 101
5.1.3 Parity Error Detection and Generation ..................................................... 101
5.1.4 PCIRST# ............................................................................................. 101
Intel ® ICH7 Family Datasheet 3
4. 5.1.5 Peer Cycles .......................................................................................... 102
5.1.6 PCI-to-PCI Bridge Model ........................................................................ 102
5.1.7 IDSEL to Device Number Mapping ........................................................... 103
5.1.8 Standard PCI Bus Configuration Mechanism.............................................. 103
5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) (Desktop and Mobile Only) .......... 103
5.2.1 Interrupt Generation ............................................................................. 103
5.2.2 Power Management............................................................................... 104
5.2.2.1 S3/S4/S5 Support ................................................................... 104
5.2.2.2 Resuming from Suspended State ............................................... 104
5.2.2.3 Device Initiated PM_PME Message ............................................. 104
5.2.2.4 SMI/SCI Generation................................................................. 105
5.2.3 SERR# Generation ................................................................................ 105
5.2.4 Hot-Plug .............................................................................................. 106
5.2.4.1 Presence Detection .................................................................. 106
5.2.4.2 Message Generation ................................................................ 106
5.2.4.3 Attention Button Detection ....................................................... 107
5.2.4.4 SMI/SCI Generation................................................................. 107
5.3 LAN Controller (B1:D8:F0) (Desktop and Mobile Only) .......................................... 108
5.3.1 LAN Controller PCI Bus Interface............................................................. 108
5.3.1.1 Bus Slave Operation ................................................................ 109
5.3.1.2 CLKRUN# Signal (Mobile Only).................................................. 110
5.3.1.3 PCI Power Management ........................................................... 110
5.3.1.4 PCI Reset Signal...................................................................... 110
5.3.1.5 Wake-Up Events...................................................................... 111
5.3.1.6 Wake on LAN* (Preboot Wake-Up) ............................................. 112
5.3.2 Serial EEPROM Interface ........................................................................ 112
5.3.3 CSMA/CD Unit ...................................................................................... 113
5.3.3.1 Full Duplex ............................................................................. 113
5.3.3.2 Flow Control ........................................................................... 113
5.3.3.3 VLAN Support ......................................................................... 113
5.3.4 Media Management Interface ................................................................. 113
5.3.5 TCO Functionality ................................................................................. 114
5.3.5.1 Advanced TCO Mode ................................................................ 114
5.4 Alert Standard Format (ASF) (Desktop and Mobile Only) ....................................... 115
5.4.1 ASF Management Solution Features/Capabilities ....................................... 116
5.4.2 ASF Hardware Support .......................................................................... 117
5.4.2.1 Intel® 82562EM/EX ................................................................. 117
5.4.2.2 EEPROM (256x16, 1 MHz) ........................................................ 117
5.4.2.3 Legacy Sensor SMBus Devices .................................................. 117
5.4.2.4 Remote Control SMBus Devices ................................................. 117
5.4.2.5 ASF Sensor SMBus Devices....................................................... 117
5.4.3 ASF Software Support ........................................................................... 118
5.5 LPC Bridge (w/ System and Management Functions) (D31:F0) ............................... 118
5.5.1 LPC Interface ....................................................................................... 118
5.5.1.1 LPC Cycle Types ...................................................................... 119
5.5.1.2 Start Field Definition ................................................................ 119
5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR) ..................................... 120
5.5.1.4 SIZE...................................................................................... 120
5.5.1.5 SYNC..................................................................................... 121
5.5.1.6 SYNC Time-Out ....................................................................... 121
5.5.1.7 SYNC Error Indication .............................................................. 121
5.5.1.8 LFRAME# Usage...................................................................... 122
5.5.1.9 I/O Cycles .............................................................................. 122
5.5.1.10 Bus Master Cycles ................................................................... 122
5.5.1.11 LPC Power Management ........................................................... 122
5.5.1.12 Configuration and Intel® ICH7 Implications................................. 123
5.5.2 SERR# Generation ................................................................................ 123
4 Intel ® ICH7 Family Datasheet
5. 5.6 DMA Operation (D31:F0) .................................................................................. 124
5.6.1 Channel Priority ................................................................................... 124
5.6.1.1 Fixed Priority.......................................................................... 125
5.6.1.2 Rotating Priority ..................................................................... 125
5.6.2 Address Compatibility Mode ................................................................... 125
5.6.3 Summary of DMA Transfer Sizes ............................................................. 125
5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count by
Words ................................................................................... 126
5.6.4 Autoinitialize........................................................................................ 126
5.6.5 Software Commands............................................................................. 126
5.7 LPC DMA (Desktop and Mobile Only) .................................................................. 127
5.7.1 Asserting DMA Requests........................................................................ 127
5.7.2 Abandoning DMA Requests .................................................................... 127
5.7.3 General Flow of DMA Transfers ............................................................... 128
5.7.4 Terminal Count .................................................................................... 128
5.7.5 Verify Mode ......................................................................................... 128
5.7.6 DMA Request Deassertion...................................................................... 129
5.7.7 SYNC Field / LDRQ# Rules ..................................................................... 129
5.8 8254 Timers (D31:F0) ..................................................................................... 130
5.8.1 Timer Programming .............................................................................. 131
5.8.2 Reading from the Interval Timer............................................................. 132
5.8.2.1 Simple Read........................................................................... 132
5.8.2.2 Counter Latch Command.......................................................... 132
5.8.2.3 Read Back Command .............................................................. 132
5.9 8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 133
5.9.1 Interrupt Handling................................................................................ 134
5.9.1.1 Generating Interrupts.............................................................. 134
5.9.1.2 Acknowledging Interrupts ........................................................ 134
5.9.1.3 Hardware/Software Interrupt Sequence ..................................... 135
5.9.2 Initialization Command Words (ICWx) ..................................................... 135
5.9.2.1 ICW1 .................................................................................... 135
5.9.2.2 ICW2 .................................................................................... 136
5.9.2.3 ICW3 .................................................................................... 136
5.9.2.4 ICW4 .................................................................................... 136
5.9.3 Operation Command Words (OCW) ......................................................... 136
5.9.4 Modes of Operation .............................................................................. 136
5.9.4.1 Fully Nested Mode................................................................... 136
5.9.4.2 Special Fully-Nested Mode........................................................ 137
5.9.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 137
5.9.4.4 Specific Rotation Mode (Specific Priority).................................... 137
5.9.4.5 Poll Mode ............................................................................... 137
5.9.4.6 Cascade Mode ........................................................................ 138
5.9.4.7 Edge and Level Triggered Mode................................................. 138
5.9.4.8 End of Interrupt (EOI) Operations ............................................. 138
5.9.4.9 Normal End of Interrupt........................................................... 138
5.9.4.10 Automatic End of Interrupt Mode .............................................. 138
5.9.5 Masking Interrupts ............................................................................... 139
5.9.5.1 Masking on an Individual Interrupt Request ................................ 139
5.9.5.2 Special Mask Mode.................................................................. 139
5.9.6 Steering PCI Interrupts ......................................................................... 139
5.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 140
5.10.1 Interrupt Handling................................................................................ 140
5.10.2 Interrupt Mapping ................................................................................ 140
5.10.3 PCI / PCI Express* Message-Based Interrupts .......................................... 141
5.10.4 Front Side Bus Interrupt Delivery ........................................................... 141
5.10.4.1 Edge-Triggered Operation......................................................... 142
Intel ® ICH7 Family Datasheet 5
6. 5.10.4.2 Level-Triggered Operation......................................................... 142
5.10.4.3 Registers Associated with Front Side Bus Interrupt Delivery .......... 142
5.10.4.4 Interrupt Message Format ........................................................ 142
5.11 Serial Interrupt (D31:F0) .................................................................................. 143
5.11.1 Start Frame ......................................................................................... 143
5.11.2 Data Frames ........................................................................................ 144
5.11.3 Stop Frame .......................................................................................... 144
5.11.4 Specific Interrupts Not Supported via SERIRQ........................................... 144
5.11.5 Data Frame Format ............................................................................... 145
5.12 Real Time Clock (D31:F0) ................................................................................. 146
5.12.1 Update Cycles ...................................................................................... 146
5.12.2 Interrupts ............................................................................................ 147
5.12.3 Lockable RAM Ranges............................................................................ 147
5.12.4 Century Rollover ................................................................................... 147
5.12.5 Clearing Battery-Backed RTC RAM ........................................................... 147
5.13 Processor Interface (D31:F0) ............................................................................ 149
5.13.1 Processor Interface Signals .................................................................... 149
5.13.1.1 A20M# (Mask A20).................................................................. 149
5.13.1.2 INIT# (Initialization)................................................................ 150
5.13.1.3 FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore Numeric
Error) .................................................................................... 150
5.13.1.4 NMI (Non-Maskable Interrupt) .................................................. 151
5.13.1.5 Stop Clock Request and CPU Sleep (STPCLK# and CPUSLP#) ........ 151
5.13.1.6 CPU Power Good (CPUPWRGOOD) ............................................. 151
5.13.1.7 Deeper Sleep (DPSLP#) (Mobile/Ultra Mobile Only) ...................... 151
5.13.2 Dual-Processor Issues (Desktop Only) ..................................................... 152
5.13.2.1 Signal Differences ................................................................... 152
5.13.2.2 Power Management ................................................................. 152
5.14 Power Management (D31:F0) ............................................................................ 153
5.14.1 Features .............................................................................................. 153
5.14.2 Intel® ICH7 and System Power States ..................................................... 153
5.14.3 System Power Planes ............................................................................ 156
5.14.4 SMI#/SCI Generation ............................................................................ 156
5.14.4.1 PCI Express* SCI (Desktop and Mobile Only) .............................. 159
5.14.4.2 PCI Express* Hot-Plug (Desktop and Mobile Only) ....................... 159
5.14.5 Dynamic Processor Clock Control ............................................................ 159
5.14.5.1 Transition Rules among S0/Cx and Throttling States..................... 160
5.14.5.2 Deferred C3/C4 (Mobile/Ultra Mobile Only) ................................. 161
5.14.5.3 POPUP (Auto C3/C4 to C2) (Mobile/Ultra Mobile Only) .................. 161
5.14.5.4 POPDOWN (Auto C2 to C3/C4) (Mobile/Ultra Mobile Only) ............. 161
5.14.6 Dynamic PCI Clock Control (Mobile/Ultra Mobile Only)................................ 161
5.14.6.1 Conditions for Checking the PCI Clock ........................................ 162
5.14.6.2 Conditions for Maintaining the PCI Clock..................................... 162
5.14.6.3 Conditions for Stopping the PCI Clock ........................................ 162
5.14.6.4 Conditions for Re-Starting the PCI Clock ..................................... 162
5.14.6.5 LPC Devices and CLKRUN# (Mobile and Ultra Mobile Only) ............ 162
5.14.7 Sleep States ........................................................................................ 163
5.14.7.1 Sleep State Overview............................................................... 163
5.14.7.2 Initiating Sleep State ............................................................... 163
5.14.7.3 Exiting Sleep States................................................................. 163
5.14.7.4 PCI Express* WAKE# Signal and PME Event Message (
Desktop and Mobile only) ......................................................... 165
5.14.7.5 Sx-G3-Sx, Handling Power Failures ............................................ 165
5.14.8 Thermal Management............................................................................ 166
5.14.8.1 THRM# Signal......................................................................... 166
5.14.8.2 Processor Initiated Passive Cooling ............................................ 166
5.14.8.3 THRM# Override Software Bit ................................................... 167
6 Intel ® ICH7 Family Datasheet
7. 5.14.8.4 Active Cooling ........................................................................ 167
5.14.9 Event Input Signals and Their Usage ....................................................... 167
5.14.9.1 PWRBTN# (Power Button) ........................................................ 167
5.14.9.2 RI# (Ring Indicator)................................................................ 168
5.14.9.3 PME# (PCI Power Management Event) ....................................... 169
5.14.9.4 SYS_RESET# Signal ................................................................ 169
5.14.9.5 THRMTRIP# Signal.................................................................. 169
5.14.9.6 BM_BUSY# (Mobile/Ultra Mobile Only) ....................................... 170
5.14.10ALT Access Mode .................................................................................. 170
5.14.10.1Write Only Registers with Read Paths in ALT Access Mode............. 171
5.14.10.2PIC Reserved Bits ................................................................... 173
5.14.10.3Read Only Registers with Write Paths in ALT Access Mode............. 173
5.14.11System Power Supplies, Planes, and Signals ............................................ 173
5.14.11.1Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5# ......... 173
5.14.11.2SLP_S4# and Suspend-To-RAM Sequencing ................................ 174
5.14.11.3PWROK Signal ........................................................................ 174
5.14.11.4CPUPWRGD Signal .................................................................. 175
5.14.11.5VRMPWRGD Signal.................................................................. 175
5.14.11.6BATLOW# (Battery Low) (Mobile/Ultra Mobile Only)..................... 175
5.14.11.7Controlling Leakage and Power Consumption during Low-Power
States ................................................................................... 175
5.14.12Clock Generators.................................................................................. 176
5.14.12.1Clock Control Signals from Intel® ICH7 to Clock
Synthesizer (Mobile/Ultra Mobile Only)....................................... 176
5.14.13Legacy Power Management Theory of Operation ....................................... 177
5.14.13.1APM Power Management (Desktop Only) .................................... 177
5.14.13.2Mobile APM Power Management (Mobile/Ultra Mobile Only) ........... 177
5.15 System Management (D31:F0).......................................................................... 178
5.15.1 Theory of Operation.............................................................................. 178
5.15.1.1 Detecting a System Lockup ...................................................... 178
5.15.1.2 Handling an Intruder ............................................................... 178
5.15.1.3 Detecting Improper Firmware Hub Programming ......................... 179
5.15.2 Heartbeat and Event Reporting via SMBus (Desktop and Mobile Only) ......... 179
5.16 IDE Controller (D31:F1) ................................................................................... 183
5.16.1 PIO Transfers ....................................................................................... 183
5.16.1.1 PIO IDE Timing Modes ............................................................. 184
5.16.1.2 IORDY Masking....................................................................... 184
5.16.1.3 PIO 32-Bit IDE Data Port Accesses ............................................ 184
5.16.1.4 PIO IDE Data Port Prefetching and Posting ................................. 185
5.16.2 Bus Master Function ............................................................................. 185
5.16.2.1 Physical Region Descriptor Format............................................. 185
5.16.2.2 Bus Master IDE Timings ........................................................... 186
5.16.2.3 Interrupts .............................................................................. 186
5.16.2.4 Bus Master IDE Operation ........................................................ 187
5.16.2.5 Error Conditions...................................................................... 188
5.16.3 Ultra ATA/100/66/33 Protocol................................................................. 188
5.16.3.1 Operation .............................................................................. 189
5.16.4 Ultra ATA/33/66/100 Timing .................................................................. 190
5.16.5 ATA Swap Bay...................................................................................... 190
5.16.6 SMI Trapping ....................................................................................... 190
5.17 SATA Host Controller (D31:F2) (Desktop and Mobile Only) .................................... 191
5.17.1 Theory of Operation.............................................................................. 192
5.17.1.1 Standard ATA Emulation .......................................................... 192
5.17.1.2 48-Bit LBA Operation............................................................... 192
5.17.2 SATA Swap Bay Support ........................................................................ 193
5.17.3 Intel® Matrix Storage Technology Configuration (Intel® ICH7R, ICH7DH,
and ICH7-M DH Only) ........................................................................... 193
Intel ® ICH7 Family Datasheet 7
8. 5.17.3.1 Intel® Matrix Storage Manager RAID Option ROM ........................ 194
5.17.4 Power Management Operation ................................................................ 194
5.17.4.1 Power State Mappings.............................................................. 194
5.17.4.2 Power State Transitions ............................................................ 195
5.17.4.3 SMI Trapping (APM) ................................................................. 196
5.17.5 SATA LED ............................................................................................ 196
5.17.6 AHCI Operation (Intel® ICH7R, ICH7DH, and Mobile Only) ......................... 196
5.17.7 Serial ATA Reference Clock Low Power Request (SATACLKREQ#) ................. 197
5.18 High Precision Event Timers .............................................................................. 197
5.18.1 Timer Accuracy..................................................................................... 197
5.18.2 Interrupt Mapping................................................................................. 198
5.18.3 Periodic vs. Non-Periodic Modes .............................................................. 198
5.18.4 Enabling the Timers .............................................................................. 199
5.18.5 Interrupt Levels.................................................................................... 199
5.18.6 Handling Interrupts............................................................................... 199
5.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 200
5.19 USB UHCI Host Controllers (D29:F0, F1, F2, and F3) ............................................ 200
5.19.1 Data Structures in Main Memory ............................................................. 200
5.19.2 Data Transfers to/from Main Memory ....................................................... 200
5.19.3 Data Encoding and Bit Stuffing ............................................................... 200
5.19.4 Bus Protocol......................................................................................... 200
5.19.4.1 Bit Ordering............................................................................ 200
5.19.4.2 SYNC Field ............................................................................. 201
5.19.4.3 Packet Field Formats................................................................ 201
5.19.4.4 Address Fields......................................................................... 201
5.19.4.5 Frame Number Field ................................................................ 201
5.19.4.6 Data Field .............................................................................. 201
5.19.4.7 Cyclic Redundancy Check (CRC) ................................................ 201
5.19.5 Packet Formats..................................................................................... 201
5.19.6 USB Interrupts ..................................................................................... 201
5.19.6.1 Transaction-Based Interrupts .................................................... 202
5.19.6.2 Non-Transaction Based Interrupts .............................................. 203
5.19.7 USB Power Management ........................................................................ 204
5.19.8 USB Legacy Keyboard Operation ............................................................. 204
5.20 USB EHCI Host Controller (D29:F7).................................................................... 207
5.20.1 EHC Initialization .................................................................................. 207
5.20.1.1 BIOS Initialization ................................................................... 207
5.20.1.2 Driver Initialization .................................................................. 207
5.20.1.3 EHC Resets............................................................................. 208
5.20.2 Data Structures in Main Memory ............................................................. 208
5.20.3 USB 2.0 Enhanced Host Controller DMA ................................................... 208
5.20.4 Data Encoding and Bit Stuffing ............................................................... 208
5.20.5 Packet Formats..................................................................................... 208
5.20.6 USB 2.0 Interrupts and Error Conditions .................................................. 209
5.20.6.1 Aborts on USB 2.0-Initiated Memory Reads................................. 209
5.20.7 USB 2.0 Power Management .................................................................. 210
5.20.7.1 Pause Feature ......................................................................... 210
5.20.7.2 Suspend Feature ..................................................................... 210
5.20.7.3 ACPI Device States .................................................................. 210
5.20.7.4 ACPI System States................................................................. 211
5.20.7.5 Mobile/Ultra Mobile Only Considerations ..................................... 211
5.20.8 Interaction with UHCI Host Controllers..................................................... 211
5.20.8.1 Port-Routing Logic ................................................................... 211
5.20.8.2 Device Connects ..................................................................... 213
5.20.8.3 Device Disconnects.................................................................. 213
5.20.8.4 Effect of Resets on Port-Routing Logic ........................................ 214
8 Intel ® ICH7 Family Datasheet
9. 5.20.9 USB 2.0 Legacy Keyboard Operation ....................................................... 214
5.20.10USB 2.0 Based Debug Port .................................................................... 214
5.20.10.1 Theory of Operation ............................................................... 215
5.21 SMBus Controller (D31:F3) ............................................................................... 219
5.21.1 Host Controller..................................................................................... 220
5.21.1.1 Command Protocols ................................................................ 220
5.21.2 Bus Arbitration..................................................................................... 224
5.21.3 Bus Timing .......................................................................................... 224
5.21.3.1 Clock Stretching ..................................................................... 224
5.21.3.2 Bus Time Out (Intel® ICH7 as SMBus Master)............................. 224
5.21.4 Interrupts / SMI#................................................................................. 225
5.21.5 SMBALERT# ........................................................................................ 226
5.21.6 SMBus CRC Generation and Checking...................................................... 226
5.21.7 SMBus Slave Interface .......................................................................... 226
5.21.7.1 Format of Slave Write Cycle ..................................................... 227
5.21.7.2 Format of Read Command........................................................ 229
5.21.7.3 Format of Host Notify Command ............................................... 231
5.22 AC ’97 Controller (Audio D30:F2, Modem D30:F3) (Desktop and Mobile Only) ......... 232
5.22.1 PCI Power Management ........................................................................ 234
5.22.2 AC-Link Overview ................................................................................. 234
5.22.2.1 Register Access ...................................................................... 236
5.22.3 AC-Link Low Power Mode....................................................................... 237
5.22.3.1 External Wake Event ............................................................... 238
5.22.4 AC ’97 Cold Reset................................................................................. 239
5.22.5 AC ’97 Warm Reset............................................................................... 239
5.22.6 Hardware Assist to Determine ACZ_SDIN Used Per Codec .......................... 239
5.23 Intel® High Definition Audio Overview ................................................................ 240
5.23.1 Intel® High Definition Audio Docking (Mobile Only) ................................... 240
5.23.1.1 Dock Sequence....................................................................... 240
5.23.1.2 Exiting D3/CRST# when Docked ............................................... 241
5.23.1.3 Cold Boot/Resume from S3 When Docked .................................. 242
5.23.1.4 Undock Sequence ................................................................... 242
5.23.1.5 Interaction Between Dock/Undock and Power Management
States ................................................................................... 243
5.23.1.6 Relationship between AZ_DOCK_RST# and AZ_RST# .................. 243
5.24 Intel® Active Management Technology (Intel® AMT) (Desktop and Mobile Only)....... 244
5.24.1 Intel® AMT Features ............................................................................. 244
5.24.2 Intel® AMT Requirements ...................................................................... 244
5.25 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) .................................. 245
5.25.1 SPI Arbitration between Intel® ICH7 and Intel PRO 82573E ....................... 245
5.25.2 Flash Device Configurations ................................................................... 245
5.25.3 SPI Device Compatibility Requirements ................................................... 246
5.25.3.1 Intel® ICH7 SPI Based BIOS Only Configuration Requirements
(Non-Shared Flash Configuration) ............................................. 246
5.25.3.2 Intel® ICH7 with Intel® PRO 82573E with Intel AMT Firmware
Configuration Requirements (Shared Flash Configuration) ............ 246
5.25.4 Intel® ICH7 Compatible Command Set .................................................... 247
5.25.4.1 Required Command Set for Inter Operability............................... 247
5.25.4.2 Recommended Standard Commands.......................................... 247
5.25.4.3 Multiple Page Write Usage Model ............................................... 248
5.25.5 Flash Protection ................................................................................... 248
5.25.5.1 BIOS Range Write Protection .................................................... 248
5.25.5.2 SMI# Based Global Write Protection .......................................... 249
5.25.5.3 Shared Flash Address Range Protection...................................... 249
5.26 Intel® Quick Resume Technology (Digital Home Only) .......................................... 249
5.26.1 Visual Off ............................................................................................ 249
Intel ® ICH7 Family Datasheet 9
10. 5.26.2 CE-like On/Off ...................................................................................... 249
5.26.3 Intel® Quick Resume Technology Signals (ICH7DH Only)............................ 250
5.26.4 Power Button Sequence (ICH7DH Only) ................................................... 250
5.27 Feature Capability Mechanism ........................................................................... 251
6 Register and Memory Mapping ............................................................................... 253
6.1 PCI Devices and Functions ................................................................................ 254
6.2 PCI Configuration Map ...................................................................................... 255
6.3 I/O Map.......................................................................................................... 255
6.3.1 Fixed I/O Address Ranges ...................................................................... 255
6.3.2 Variable I/O Decode Ranges ................................................................... 258
6.4 Memory Map ................................................................................................... 259
6.4.1 Boot-Block Update Scheme .................................................................... 261
7 Chipset Configuration Registers ............................................................................. 263
7.1 Chipset Configuration Registers (Memory Space).................................................. 263
7.1.1 VCH—Virtual Channel Capability Header Register ...................................... 265
7.1.2 VCAP1—Virtual Channel Capability #1 Register ......................................... 265
7.1.3 VCAP2—Virtual Channel Capability #2 Register ......................................... 266
7.1.4 PVC—Port Virtual Channel Control Register............................................... 266
7.1.5 PVS—Port Virtual Channel Status Register ................................................ 266
7.1.6 V0CAP—Virtual Channel 0 Resource Capability Register .............................. 267
7.1.7 V0CTL—Virtual Channel 0 Resource Control Register .................................. 267
7.1.8 V0STS—Virtual Channel 0 Resource Status Register................................... 268
7.1.9 V1CAP—Virtual Channel 1 Resource Capability Register .............................. 268
7.1.10 V1CTL—Virtual Channel 1 Resource Control Register .................................. 269
7.1.11 V1STS—Virtual Channel 1 Resource Status Register................................... 269
7.1.12 RCTCL—Root Complex Topology Capabilities List Register ........................... 270
7.1.13 ESD—Element Self Description Register ................................................... 270
7.1.14 ULD—Upstream Link Descriptor Register .................................................. 270
7.1.15 ULBA—Upstream Link Base Address Register ............................................ 271
7.1.16 RP1D—Root Port 1 Descriptor Register..................................................... 271
7.1.17 RP1BA—Root Port 1 Base Address Register ............................................... 271
7.1.18 RP2D—Root Port 2 Descriptor Register..................................................... 272
7.1.19 RP2BA—Root Port 2 Base Address Register ............................................... 272
7.1.20 RP3D—Root Port 3 Descriptor Register..................................................... 272
7.1.21 RP3BA—Root Port 3 Base Address Register ............................................... 273
7.1.22 RP4D—Root Port 4 Descriptor Register..................................................... 273
7.1.23 RP4BA—Root Port 4 Base Address Register ............................................... 273
7.1.24 HDD—Intel® High Definition Audio Descriptor Register............................... 274
7.1.25 HDBA—Intel® High Definition Audio Base Address Register......................... 274
7.1.26 RP5D—Root Port 5 Descriptor Register..................................................... 274
7.1.27 RP5BA—Root Port 5 Base Address Register ............................................... 275
7.1.28 RP6D—Root Port 6 Descriptor Register..................................................... 275
7.1.29 RP6BA—Root Port 6 Base Address Register ............................................... 275
7.1.30 ILCL—Internal Link Capabilities List Register ............................................. 276
7.1.31 LCAP—Link Capabilities Register ............................................................. 276
7.1.32 LCTL—Link Control Register.................................................................... 277
7.1.33 LSTS—Link Status Register .................................................................... 277
7.1.34 RPC—Root Port Configuration Register ..................................................... 278
7.1.35 RPFN—Root Port Function Number for PCI Express Root Ports
(Desktop and Mobile only) ..................................................................... 279
7.1.36 TRSR—Trap Status Register .................................................................... 280
7.1.37 TRCR—Trapped Cycle Register ................................................................ 280
7.1.38 TWDR—Trapped Write Data Register ........................................................ 280
7.1.39 IOTRn — I/O Trap Register (0-3)............................................................. 281
10 Intel ® ICH7 Family Datasheet