This is an introduction to the EXAR 600KHZ High Input Voltage Step-Down DC/DC Voltage Regulator SP7656 Power Blox
Welcome to the training module on the SP7656 . This training module gives an overview function and operation of the device and application details.
The SP7656 is a PWM controlled step down (buck) voltage mode regulator co-packaged with a P-Channel FET. It operates from 4.5V to 29V making it suitable for 5V, 12V and 24V applications. The programmable over-current protection is based on internal FET resistance sensing and allows setting the over-current protection value up to a 300mV threshold.
The SP7656 PowerBlox is a fixed frequency, voltage mode, non-synchronous PWM controller co-packaged with a P-Channel FET. SP7656 has Type-2 internal compensation for use with Electrolytic/Tantalum output capacitors. A precision 0.6V reference, present on the positive terminal of the internal error amplifier, permits programming of the output voltage down to 0.6V via the FB pin. The output of the Error Amplifier is internally compared to a feed-forward (VIN/5 peak-to-peak) ramp and generates the PWM control. Timing is governed by an internal oscillator that sets the PWM frequency at 600kHz.
The SP7656 contains useful protection features. Over-current protection is based on the internal MOSFET Rds(on) and is programmable via a resistor placed between ISET and LX node. Under-Voltage Lock-Out (UVLO) ensures that the controller starts functioning only when sufficient voltage exists for powering IC’s internal circuitry. The over-current protection circuit functions by monitoring the voltage across the internal P-Channel FET. The FET has nominal Rds(on) of 0.06Ω, assuming no temperature rise.
The SP7656 includes Type-2 internal compensation components for loop compensation. External compensation components are not required for systems with tantalum or aluminum electrolytic output capacitors with sufficiently high ESR. The above condition requires the ESR zero to be at a lower frequency than the double-pole from the LC filter. If this condition is not met, Type-3 compensation should be used and can be accomplished by placing a series RC combination in parallel with R1 as shown.
This page gives information about programming the output voltage, soft start, and function using the VFB pin.
This Page gives information about input and output capacitance selection for the SP7656 device. Voltage rating is nominally selected to be approximately twice the input voltage. Input voltage ripple has three components: ESR and ESL cause a step voltage drop upon turn on of the MOSFET. The Output capacitor is selected for voltage rating, capacitance and Equivalent Series Resistance (ESR).
The SP7656ER is designed with an accurate 2.0% reference over line, load and temperature. The graph data shows a typical SP7656 evaluation board efficiency and regulation plots, with efficiencies up to 87% and output currents up to 4A. The output voltage ripple of less than 6.6mV at full load and the LX node are shown. All waveforms were taken under 12V to 3.3V conversion.
The SP7656 Evaluation Board design was optimized for 12V down conversion to 3.3V, changes of output voltage and/or input voltage will alter performance from the data given in the Power Supply data section. Connect a Load between the VOUT and GND posts, again using short leads to minimize parasitic inductance and voltage drop. It’s best to GND reference the scope and digital meters using a single GND post in the output of the board. The SP7656 Evaluation Board has been tested and delivered with the output set to 3.3V, by simply changing one resistor, R2, the SP7656 can be set to other output voltages.
The SP7656 is optimized to provide superior performance for low duty cycle applications. For applications with output voltages below 9V, the device will operate normally at the expected 600kHz switching frequency for conversions with less than 50% duty cycle. For applications with output voltages below 9V and greater than 50% duty cycle, the device will enter into a pulse skipping mode. This is due to the FB voltage to internal ramp voltage ratio of the device, and is an intended behaviour from an architecture optimized for superior performance in low duty cycle conversion applications and results in a small increase in output ripple voltage for any given circuit.
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