Slides presented at the FlexTiles Workshop at FPL'2014. Presentation #7: FlexTiles Emulation platform FlexTiles is a heterogeneous many-core platform reconfigurable at run-time developed within an FP7 project.

1. www.flextiles.eu
FlexTiles
Prof. Dr.-Ing Michael Hübner
Ruhr-University Bochum (RUB)
FlexTiles Workshop at FPL 2014
FPGA-Based Emulation of the FlexTiles Platform

2. 2 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
Global View
GPP Node
AI
DSP
FPGA Fabric
NI
Network-on-Chip (NoC)
NI
NI
AI
NI
Reconfig. Control
DDR Node
NI
Tile
Tile
GPP Node
NI
I/O
NI
eFPGA

3. 3 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
Development Platform
Software Emulator
Based on Open Virtual Platform
Enable Software prototyping
Hardware Emulator
FlexTiles Development Platform
Based on 2 Virtex-6 FPGAs
Hardware design by TU/e
Enable Hw/Sw prototyping

4. 4 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
Development Platform
System Components
GPP Node
MicroBlaze soft-core processors
Network on Chip
Nodes connected via Network Interfaces
Network Interface
Device Transport Layer (DTL) protocol
Accelerator Interface
Newly developed within this project
Accelerators
Micro-programmed
Data-flow
GPP Node
AI
Accelerator
NI
NoC
NI

5. 5 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
Network on Chip
Network on Chip
AElite NoC
Network Interface
Main Task
Data into packets  NoC
NoC  data out of packets
Device Transport Layer
Master / Slave
Data flow
Load / Store
Stream
GPP Node
AI
Accelerator
NI
NoC
NI

6. 6 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
Accelerator Interface
Main Tasks
Control accelerators
Provide a unique interface
Components
Accelerator control
Protocol parser
GPP Node
AI
Accelerator
NI
NoC
NI
AC

7. 7 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
AI : DTL-To-AI
Device Transaction Layer (DTL)
Command (dtl_cmd)
Write (dtl_wr)
Read (dtl_rd)
DTL-To-AI Structure
GPP Node
AI
Accelerator
NI
NoC
NI
DTL2AI
AC

8. 8 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
AI : Accelerator Control
Accelerator Control Structure
GPP Node
AI
Accelerator
NI
NoC
NI
DTL2AI
AC
in
out

9. 9 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
Accelerators
Accelerator Types
Micro-programmed: FlexTiles DSP
Data-flow: Accelerators on eFPGA
Lite Accelerator
Example/Test Application
Implements
2 register banks
3 FIFOs
Adding two sequential values
GPP Node
AI
Accelerator
NI
NoC
NI

10. 10 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
Software Functions
Accelerator Software Functions
send_rqst
(int acc_number, int size, int ch_id, int addr, char type)
send_data
(int acc_number, int size, int ch_id, int addr, int* array)
read_data
(int acc_number, int size, int addr, int* array)
write_register
(int acc_number, int ch_id, int addr, int value)
read_register
(int acc_number, char regis)
GPP Node
AI
Accelerator
NI
NoC
NI

11. 11 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
Development Platform Configuration
Xilinx Platform Studio Project
TUe Platform configured via XML file
Xilinx Microprocessor Project file (XMP) Platform Configuration
User Constraint File (UCF)
Microprocessor Hardware Specification (MHS)
Microprocessor Software Specification (MSS)

12. 12 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
Adding Accelerators
Accelerator Integration
Peripheral Core (PCORE)
Add Accelerator files to pcore directory
Add Accelerator entry to MHS Configuration Files
Black Box Definition file (BBD)
Peripheral Analyze Order file (PAO)
Microprocessor Peripheral Definition (MPD)

13. 13 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
Implementation
XPS Command Line Mode
xps -nw -scr system.tcl system.xmp Simple Design:
GPP
AI
+
Acc
Debug
Monitor
NoC

14. 14 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
Implementation Results
Results
Standalone platform
Occupied Slices: 5%
IOB: 1%
RAMB36E1: 13%
RAMB18E1: 0%
BUFG: 9%
Platform with lite accelerator
Occupied Slices: 7%
IOB: 1%
RAMB36E1: 13%
RAMB18E1: 1%
BUFG: 12%
GPP Node
NI
NoC
Monitor Node
GPP Node
AI
Lite Accelerator
NI
NoC
NI
Monitor Node

15. 15 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
Implementation Results
Results
Platform with DSP
Occupied Slices: 62%
IOB: 1%
RAMB36E1: 15%
RAMB18E1: 1%
BUFG: 9%
GPP Node
AI
DSP
NI
NoC
NI
Monitor Node

16. 16 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
Challenges
Platform with DSP
Unroutable Signals (Rats Nests) Colors
Monitor: yellow
GPP: cyan
NoC: purple
AI: green
DSP: red

17. 17 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
Summary
Emulator Goal
Run demo application like optical flow
NoC
GPP Node
NI
NI
GPP Node
GPP Node
NI
NI
GPP Node
NI
NI
NI
NI
AI
Acc
AI
Acc
Acc
AI
Acc
AI
NoC
AURORA

18. 18 /
The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution,
copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
18
Many Thanks for Your Attention!
www.flextiles.eu
Benedikt.Janssen@rub.de
The last Slide