FlexTiles is a FP7 Project with the goal of designing a tool-chain for the design of a 3D SoC and prototype on a FPGA Development Platform. This presentation covers the "why, how, when and where" of the Project that will complete in Year 2015

1. www.thalesgroup.com
Research & Technology
2014/07/14/PhM
Designing Sophisticated Signal
Processing Architectures for
challenging real-time applications
The FP7 - FlexTiles project
www.flextiles.eu
Philippe MILLET, PhD, AHS 2014
philippe.millet@thalesgroup.com
www.thalesgroup.com

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2014/07/14/PhM
FlexTiles Workshop
FlexTiles : Self-Adaptive Heterogeneous Many-Core
Technology Based on Flexible Tiles
Workshop On Friday 18th in the morning (9:00 - 13:00)
• 3-D Stacked Chip Technology and Strategies for Optimal Usage of
Through Silicon Vias (TSV)
• FlexTiles Simulating Environment Based on Open Virtual Platform (OVP)
• Low-Power DSP Accelerator Embedded in a Heterogeneous Many-Core
Architecture.
• Dynamically Reconfigurable Embedded FPGA System
• FPGA-Based Emulation of FlexTiles Platform
• Demonstration: OVP Simulation of the FlexTiles Platform

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Some challenging applications within THALES
Cognitive radio
Source:
the India economy review
Adapt continuously the
frequency and protocol to
available ones
Avoid jammers or
obfuscated
communications

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Some challenging applications within THALES
Smart camera
Highway: follow cars, detect traffic jam or accidents
Airport : find and follow people, detect abandoned
luggage, strange or dangerous behaviours.
Dynamicity depends on the number of detections
Cameras have local
processing capability to
send data only when
something "interesting"
has been detected.

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Some challenging applications within THALES
UAV
Autonomous, take decisions
without or with low control.
React to the environment.
Self-repair.
Adapt the mission to what the UAV finds.
Activate software parts to match the actual situation.
The software is dynamically activated and mapped to the
available resources.

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Real-time embedded products at THALES
Embedded Real-Time Market
 low power consumption
 target in a range from 10W - 40W
 some products are designed with <1W (low adaptivity)
 General Purpose Processors are too hungry
 low volumes (less than 1000 pieces/year)
 designing dedicated ASIC is not an option
 long life-time (~20 years)
 Long Life No Maintenance
 hardware upgrade or retrofit must cost as little as possible
 programmable device is preferred

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Some challenging applications within THALES
Embedded Real-Time Market
 low power consumption
 low volumes
 long life-time (~20 years)
Adapt to environment  dynamicity, flexibility & dependability
Smart cameraCognitive radio UAV
We need more than static dataflow.
We need adaptability in the software
as well as in the hardware
Source:
the India economy review

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Homogeneous Manycore a solution?
One way to get high performance / watt is parallelism.
• Instead of 1 big core with high computation power but also high
power consumption, get more "smaller" cores in parallel

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Homogeneous manycores: Good at Parallelism
Parallelisation: raise computing power / lower power consumption.
Homogeneity eases programming (C-Like + tools) but:
Maximum performance only with static application.
automatic optimisation (data parallelism)
static allocation and scheduling.
Else  Average performances / No guaranty
Tilera - Tile-Gx72 – 72 cores
 C/C++
Nvidia - Kepler 2000+ cores
 OpenCL/CUDA (C like+kernels)
Kalray - MPPA - 256/1024 cores
 SigmaC (C++ like for dataflow)
source: www.tilera.com
http://www.kalray.eu
source: www.nvidia.fr

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Manycore is a main issue for the industry
 Programmability (industrial view):
 Time to market
 SW Development costs
 Reuse of legacy code
 What about Manycores?
 Homogeneous?
 Heterogeneous?

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Manycore is a main issue for the industry
 Programmability (industrial view):
 Time to market
 SW Development costs
 Reuse of legacy code
 What about Manycores?
 Homogeneous?
 Heterogeneous?
Why taking risks with Manycores ?
We want to continue like in the good days:
compile “without thinking” and get performances
(keep it as long/simple as possible) !

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Manycore
No more choice, we HAVE TO jump
ManyCores!
Problem Solved...?

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Manycore
No more choice, we HAVE TO jump
ManyCores!
Problem Solved...?
WAIT!

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Parallelisation is not enough: did we miss something?
Homogeneous?

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Challenge
PROCESSORS (GPPs)
FPGA
DSP
available architectures: already homogeneous systems
With ManyCores and integration, the
architectures are changing...

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Challenge
PROCESSORS
FPGA
DSP
Source: http://www.gamearenaph.com
Source: http://www.vision.caltech.edu
APPLICATIONS
computation demanding applications
Usual way:
put as many resources as
necessary to execute the
application in any situation.
=> hardware must allow the
hardest case to execute
Dynamicity:
=> the hardest case is
unknown
=> too costly, too heavy, too
high power consumption.

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Challenge
PROCESSORS
FPGA
DSP
Source: http://www.gamearenaph.com
Source: http://www.vision.caltech.edu
APPLICATIONS
Source: http://www.funtoosh.com
how can we fit big applications in the hardware?
How to efficiently
map complex applications
to heterogeneous many-core architectures
with limited budget
(power, performance, …)
???
LIMITED BUDGET
Source: http://www.lnci.org.au

18. www.thalesgroup.com
Research & Technology
2014/07/14/PhM
www.flextiles.eu
Philippe MILLET
philippe.millet@thalesgroup.com
Project coordinator: THALES
Funding budget: 3,670,000€
Starting date: 15/10/2011
Duration: 36 months (42)
www.thalesgroup.com

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Consortium and questions
Partners & Third
Party
Country Main scientific and
technical contributions
THALES France Infrastructure and
applications
KIT Germany Virtualisation layer
TUE Netherlands Kernel ; NoC
CSEM Switzerland DSP
CEA France NoC ; 3D stacking
UR1 France Reconfigurable technology
SUNDANCE United
Kingdom
FPGA Demonstrator
ACE Netherlands Parallelisation and
compilation Tools
RUB Germany Integration
FPGA scheduling
9 partners in 5 countries

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Did I mension our FlexTiles Workshop?
FlexTiles : Self-Adaptive Heterogeneous Many-Core
Technology Based on Flexible Tiles
Workshop On Friday 18th in the morning (9:00 - 13:00)
• 3-D Stacked Chip Technology and Strategies for Optimal Usage of
Through Silicon Vias (TSV)
• FlexTiles Simulating Environment Based on Open Virtual Platform (OVP)
• Low-Power DSP Accelerator Embedded in a Heterogeneous Many-Core
Architecture.
• Dynamically Reconfigurable Embedded FPGA System
• FPGA-Based Emulation of FlexTiles Platform
• Demonstration: OVP Simulation of the FlexTiles Platform

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2014/07/14/PhM
A Town close to Madrid

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Customized/Customizable chips vs. FPGA
Xilinx – ZYNQ : FPGA with
a dual ARM A9 core
 MPCore with reconfiguration
capabilities
ClusterCluster ClusterCluster ClusterCluster
ClusterCluster ClusterCluster ClusterCluster
ClusterCluster ClusterCluster ClusterCluster
Fabric
Controller
core
Fabric
Controller
core
Fabric
GOOD Parallelization
POOR Customization
POOR Parallelization
GOOD Customization
ST – P2012 aka STHORM
(Heterogeneous manycore fabric)
 Once done: Dedicated to a
specific domain of applications
 Affordable only for large series of
products.
Main issue: Domain dedication
idem with MPSoCs (TI-OMAPs)

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FlexTiles Proposes
A 3D stacked chip based on:
 A manycore layer
 GPPs
 DSPs
 A FPGA layer
 A 3D-NoC
GOOD Parallelization
GOOD Customization
Customization at low price
Opportunity: self adaptive capabilities
 Future application needs

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Self adaptive?
 Adapt the architecture to application requests at "real-time"
 Improve yield and extend life-time of sub-micron technologies
 Fault tolerance
 Increase energy efficiency
 give the right task to the best available processor
 finalize the mapping at runtime
 Temperature management  re-mapping
 Triplication, voting  fault / error detection
 Self-repair  re-mapping taking dead cores into account
How to program it?

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Holistic Approach: Model of Execution
Model of ComputationModel of Computation
Optimisation toolsOptimisation tools
Programming
Efficiency
Self-Adaptive
Capabilities
Relocation strategiesRelocation strategies
Model of programmationModel of programmation Flexible HardwareFlexible Hardware
Common InterfacesCommon Interfaces
Model of Execution

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Model of Execution
Master NodesMaster Nodes
Slave NodesSlave Nodes
GPP nodes
eFPGA nodes
DSP nodes
GPP Node
accelerator
node
NI
NoC
NI
Accelerator Interface (AI)
acc
requests
control
/ status
control
/ status
DMA
DMA
requests
data
Master-slave execution model
AI HW / SW independency regarding accelerator specificities

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Model of Computation & Model of Programmation
Optimisation toolsOptimisation tools
Programming
Efficiency
Self-Adaptive
Capabilities
Relocation strategiesRelocation strategies
Flexible HardwareFlexible Hardware
Common InterfacesCommon Interfaces
Model of Computation Model of ExecutionModel of Execution
Model of programmation

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: Clusters group managed
by a state management
: Cluster group input/output
ActAct ActAct
ActAct ActAct
ActAct
ActAct ActActActAct
state 1state 1
state 2state 2
state 3state 3
states managementstates management
cluster groupcluster group
event
Model of Computation & Model of Programmation
Optimisation and parallelisation tools work on static applications
find static clusters inside the applications based on SDF/CSDF MoC
Bring Dynamicity with higher hierarchical level
: actor ~ task or tasks
: static cluster
ActAct
: Cluster input/output
actor: consumes and produces
token of data with predefined
and static rules
SDF, CSDF MoC

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ActAct
sensor
data
states managementstates management
event
ActAct
state 1state 1
nopnop
state 1state 1
states managementstates management
states managementstates management
ActAct ActAct
ActAct
state 2state 2
ActAct
ActAct
states managementstates management
event
ActAct ActAct
ActAct
state 1state 1
ActAct
ActAct
states managementstates management
ActAct ActAct
ActAct
state 1state 1
ActAct
ActActs
c
a
t
t
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r
s
c
a
t
t
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r
g
a
t
h
e
r
g
a
t
h
e
r
sensor
data
cluster group 3cluster group 3
cluster group 4cluster group 4
cluster group 5cluster group 5
cluster group 2cluster group 2
cluster group 1cluster group 1 event
event
event
Model of Programmation
: Actor
: static cluster
ActAct
: Clusters group managed
by one state management
: Cluster group input/output
: Cluster input/output

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Dynamicity at cluster group level
ActAct
sensor
data
states managementstates management
event
ActAct
state 1state 1
nopnop
state 1state 1
states managementstates management
states managementstates management
ActAct ActAct
ActAct
state 2state 2
ActAct
ActAct
states managementstates management
event
ActAct ActAct
ActAct
state 1state 1
ActAct
ActAct
states managementstates management
ActAct ActAct
ActAct
state 1state 1
ActAct
ActActs
c
a
t
t
e
r
s
c
a
t
t
e
r
ActAct ActAct
ActAct
state 1.1state 1.1
ActAct
ActAct
ActAct ActAct
ActAct
state 1.2state 1.2
ActAct
ActAct
g
a
t
h
e
r
g
a
t
h
e
r
sensor
data
cluster group 3cluster group 3
cluster group 4cluster group 4
cluster group 5cluster group 5
cluster group 2cluster group 2
cluster group 1cluster group 1 event
event
event
: Actor
: static cluster
ActAct
: Clusters group managed
by one state management
: Cluster group input/output
: Cluster input/output

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Start a new part of the application
ActAct
sensor
data
states managementstates management
event
ActAct
state 1state 1
states managementstates management
states managementstates management
ActAct ActAct
ActAct
state 2state 2
ActAct
ActAct
states managementstates management
event
ActAct ActAct
ActAct
state 1state 1
ActAct
ActAct
states managementstates management
ActAct ActAct
ActAct
state 1state 1
ActAct
ActActs
c
a
t
t
e
r
s
c
a
t
t
e
r
ActAct ActAct
ActAct
state 1.1state 1.1
ActAct
ActAct
ActAct ActAct
ActAct
state 1.2state 1.2
ActAct
ActAct
g
a
t
h
e
r
g
a
t
h
e
r
sensor
data
cluster group 3cluster group 3
cluster group 4cluster group 4
cluster group 5cluster group 5
cluster group 2cluster group 2
cluster group 1cluster group 1 event
event
event
ActAct ActAct
ActAct
state 2state 2
ActAct
: Actor
: static cluster
ActAct
: Clusters group managed
by one state management
: Cluster group input/output
: Cluster input/output

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Modification of the behaviour
sensor
data
states managementstates management
event
states managementstates management
states managementstates management
ActAct ActAct
ActAct
state 2state 2
ActAct
ActAct
states managementstates management
event
ActAct ActAct
ActAct
state 1state 1
ActAct
ActAct
states managementstates management
ActAct ActAct
ActAct
state 1state 1
ActAct
ActActs
c
a
t
t
e
r
s
c
a
t
t
e
r
ActAct ActAct
ActAct
state 1.1state 1.1
ActAct
ActAct
ActAct ActAct
ActAct
state 1.2state 1.2
ActAct
ActAct
g
a
t
h
e
r
g
a
t
h
e
r
sensor
data
cluster group 3cluster group 3
cluster group 4cluster group 4
cluster group 5cluster group 5
cluster group 2cluster group 2
cluster group 1cluster group 1 event
event
event
ActAct ActAct
ActAct
state 2state 2
ActAct
ActAct ActAct
ActAct
state 2state 2
: Actor
: static cluster
ActAct
: Clusters group managed
by one state management
: Cluster group input/output
: Cluster input/output

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Modification of the parallelisation level
sensor
data
states managementstates management
event
states managementstates management
states managementstates management
ActAct ActAct
ActAct
state 2state 2
ActAct
ActAct
states managementstates management
event
ActAct ActAct
ActAct
state 1state 1
ActAct
ActAct
states managementstates management
ActAct ActAct
ActAct
state 1state 1
ActAct
ActActs
c
a
t
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s
c
a
t
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r
g
a
t
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r
g
a
t
h
e
r
sensor
data
cluster group 3cluster group 3
cluster group 4cluster group 4
cluster group 5cluster group 5
cluster group 2cluster group 2
cluster group 1cluster group 1 event
event
event
ActAct ActAct
ActAct
state 2state 2
ActAct
ActAct ActAct
ActAct
state 2state 2
: Actor
: static cluster
ActAct
: Clusters group managed
by one state management
: Cluster group input/output
: Cluster input/output

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ActAct
sensor
data
states managementstates management
event
ActAct
state 1state 1
states managementstates management
states managementstates management
ActAct ActAct
ActAct
state 2state 2
ActAct
ActAct
states managementstates management
event
ActAct ActAct
ActAct
state 1state 1
ActAct
ActAct
states managementstates management
ActAct ActAct
ActAct
state 1state 1
ActAct
ActActs
c
a
t
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r
s
c
a
t
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ActAct ActAct
ActAct
state 1.1state 1.1
ActAct
ActAct
ActAct ActAct
ActAct
state 1.2state 1.2
ActAct
ActAct
g
a
t
h
e
r
g
a
t
h
e
r
sensor
data
cluster group 3cluster group 3
cluster group 4cluster group 4
cluster group 5cluster group 5
cluster group 2cluster group 2
cluster group 1cluster group 1 event
event
event
ActAct ActAct
ActAct
state 2state 2
ActAct
Model of Programmation
: Actor
: static cluster
ActAct
: Clusters group managed
by one state management
: Cluster group input/output
: Cluster input/output

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Programming efficiency: Model of Computation
Programming
Efficiency
Self-Adaptive
Capabilities
Relocation strategiesRelocation strategies
Model of programmationModel of programmation Flexible HardwareFlexible Hardware
Common InterfacesCommon Interfaces
Model of ExecutionModel of Execution
Optimisation tools
Model of ComputationModel of Computation

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Application
(C code)
Application
(C code)
C to SpearDE
representation
Conversion (Thales)
C to SpearDE
representation
Conversion (Thales)
Data parallelisation Mapping (Thales)Data parallelisation Mapping (Thales)
Graphic input
(manual)
+
C kernels
Graphic input
(manual)
+
C kernels
Streaming optimisation
(ACE)
Streaming optimisation
(ACE)
Compilation & Link
(ACE)
Compilation & Link
(ACE)
architecture
representation
architecture
representation
Master coresMaster coresSlave coresSlave cores
Library of IPsLibrary of IPs
Tool flow and MoC
Tool flow based
Programming efficiency: Model of Computation
Binaries
Acc compiler or C2VHDL tools
(CSEM / UR1 / RUB)
Acc compiler or C2VHDL tools
(CSEM / UR1 / RUB)

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Programming efficiency: Model of Computation
Programming
Efficiency
Self-Adaptive
Capabilities
Relocation strategiesRelocation strategies
Model of programmationModel of programmation Flexible HardwareFlexible Hardware
Model of ExecutionModel of ExecutionModel of ComputationModel of Computation
Common Interfaces
Optimisation toolsOptimisation tools

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Modularity and scalability: common interfaces
Homogeneous
GPP nodes
Heterogeneous
accelerators
nodes
GPP Node
AI
DSP
Node
NI
GPP Node
NI
NoC
NI NI NI
AI AI
NI
Config. Ctrl.
DDR Ctrl.
NI
GPP Node
NI
I/O
NI
Generic
Interfaces
eFPGA Domain
(Reconfigurable HW acc.)
Dedicated
Accelerator
Node
Dedicated
Accelerator
Node

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GPP Node
AI
DSP eFPGA Domain (Reconfigurable HW acc.)
NI
GPP Node
NI
NoC
NI NI NI
AI AI
NI
Config. Ctrl.
DDR Ctrl.
NI
Tile Tile
GPP Node
NI
I/O
NI
TILE TILE
AIAI Accelerator Interface
Interpret requests from GPP
NINI
Network Interface
Interfaces a node with NoC
Modularity and scalability: common interfaces

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Relocation Strategies
Programming
Efficiency
Self-Adaptive
Capabilities
Model of programmationModel of programmation Flexible HardwareFlexible Hardware
Model of ExecutionModel of ExecutionModel of ComputationModel of Computation
Optimisation toolsOptimisation tools
Relocation Strategies
Common InterfacesCommon Interfaces

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A1.1A1.1 A2.1A2.1
A3A3
A5A5
A4A4
A1.2A1.2 A2.2A2.2
A1.3A1.3 A2.3A2.3
A1.4A1.4 A2.4A2.4
•FPGA•FPGA
•GPP•GPP
•FPGA•FPGA
A1.1A1.1 A2.1A2.1
A3A3
A5A5
A4A4
A1.2A1.2 A2.2A2.2
A1.3A1.3 A2.3A2.3
A1.4A1.4 A2.4A2.4
•DSP•DSP
•GPP•GPP
•DSP•DSP
A1.1A1.1 A2.1A2.1
A3A3
A5A5
A4A4
A1.2A1.2 A2.2A2.2
A1.3A1.3 A2.3A2.3
A1.4A1.4 A2.4A2.4
•DSP•DSP
•DSP•DSP
•DSP•DSP
timerelocation relocation relocation
Relocation Strategies

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Self-adaptation
Accelerator/Virtual Code
Dynamic
allocation / binding
DIAGNOSIS
O = F(L)
ACTION
SYSTEM
MONITORING
GPP Node
AI
DSP
Node
NI
GPP Node
NI
NoC
NI NI NI
AI AI
NI
Config. Ctrl.
DDR Ctrl.
NI
GPP Node
NI
I/O
NI
Dedicated
Accelerator
Node
Dedicated
Accelerator
Node
eFPGA Domain (Reconfigurable HW acc.)

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Flexible Hardware
Programming
Efficiency
Self-Adaptive
Capabilities
Model of programmationModel of programmation
Model of ExecutionModel of ExecutionModel of ComputationModel of Computation
Optimisation toolsOptimisation tools
Common InterfacesCommon Interfaces
Flexible Hardware
Relocation strategiesRelocation strategies

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Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
New dynamic reconfigurable technology
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
3D stacked reconfigurable layer

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Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
New dynamic reconfigurable technology
3D stacked reconfigurable layer
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
Map Accelerated functions

46. 6 /46 / 60
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Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
New dynamic reconfigurable technology
3D stacked reconfigurable layer
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
Duplicate

47. 7 /47 / 60
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Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
New dynamic reconfigurable technology
3D stacked reconfigurable layer
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
Migrate

48. 8 /48 / 60
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3D Network
Programming
Efficiency
Self-Adaptive
Capabilities
Model of programmationModel of programmation
Model of ExecutionModel of ExecutionModel of ComputationModel of Computation
Optimisation toolsOptimisation tools
Common InterfacesCommon Interfaces
Flexible Hardware
Relocation strategiesRelocation strategies
The Flexibility of the tile
is based on the capabilities
of the 3D Network

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did you say 3D?

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NoC QoS
chipchip
GPP
icache
dcache
dLMEM GPP
NI
iLMEM eFPGA
eFPGA
dLMEM eFPGA
iLMEM DSP
DSP
dLMEM DSP
DDR
NI
+
DDR
ctrl
on chip
shMEM
NI NI
control
NOC
bitstream
NOC
data
NOC
instruction
NOC
test/debug
NOC
Avoid Bus contention,
QoS depends on what you send through the NoC

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ANoC (CEA)
GALS: asynchronous logic in nodes, local synchronous cores
-highly scalable
-between nodes: no global clock, not even local clock
-power efficient and dependable
-packet switching
-wormhole protocol
-low latency

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AElite NoC (TUe)
Guaranteed levels of services and performances
Contention free routing by construction
- wormhole routing specified at design time
Globally Synchronous with time slots

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Demonstration
On a FPGA board provided by Sundance we demonstrate
the self adaptive capabilities of the solution.
An OVP simulator is also available.

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Demonstration: Building the HW platform

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FlexTiles Development Board
Virtex6
FPGA 2
Virtex6
FPGA 1
Implementation of
multicore Implementation of
accelerators
Aurora
or
Ethernet
Demonstration

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Demonstration
FlexTiles Board
FPGA 2FPGA 1
FPGA 1
N
O
C
N
I
A
I
Acc
FPGA 2
AURORA interface
AURORA interface
N
I
Multi
GPP
core
A
I Acc

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FPGA BOARDFPGA BOARD
NoC
Monitor
uBlaze
DMA
2x
uBlaze
DMA
2x
256kbyte
256kbyte
8 kbyte
8 kbyte
8 kbyte
8 kbyte
256kbyte
256kbyteTile 1
Tile 2
Host PC
Debug Link
256kbyte
Shared
Memory

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Demonstration: monitoring

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Conclusion FlexTiles … a complete platform
Virtualisation
layer
Virtualisation
layer
relocatable binary coderelocatable binary code
Parallelisation, partioningParallelisation, partioning
Application
Hardware Nodes
CompilationCompilation Synthesis, P&RSynthesis, P&R
relocatable bitstreamrelocatable bitstream
Hardware Abstraction Layer
Hardware Abstraction Layer API
Operating Library API
KernelKernel Resource
Monitoring &
Allocation
Resource
Monitoring &
Allocation
DIAGNOSIS
O = F(L)
ACTION
SYSTEM
toolchain
operating
library
heterogenous
manycore
MONITORING

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Conclusion
Parallelisation is the only way to reach HPC for low power
consumption.
But parallelism is not enough, customisation is also
necessary
 Only affordable for high volumes
Reconfigurable customisation is the solution:
 Increase accessibility to heterogeneous manycore technology
 Offers self-adaptive capabilities

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Come visit us next Friday Morning
FlexTiles : Self-Adaptive Heterogeneous Many-Core
Technology Based on Flexible Tiles
Workshop On Friday 18th morning (9:00 - 13:00)