5. Процессор нь үндсэн хэсгийн нэг бөгөөд = Datapath +
Control
Datapath нь санах байгууламжийн дээд хэсэгт
байрлах ба ж нь зарим тохиолдолд cache-уудаар
дамжих нь бий. Түүнчлэн зарим нь санах
байгууламжийг бүхэлд нь агуулдаг.
Control Signals
Control
Unit
Most processors consist of a datapath
and a control unit, with a large part of
the control unit dedicated to regulating
the interaction between the datapath
and memory.
Status
Signals
Datapath
(Processing of
data according
to instructions))
9. Өгөгдөл боловсруулалттай холбоотой бүхий л үйлдлүүдийн
гүйцэтгэл бүхий ALU хэсгийн нэгдлийг Datapath гэж ойлгоно. Энэ
нь үндсэн дараах хэсгүүдээс тогтдог:
• Data Memory
• Register File
Data Memory
• ALU
Memory Interface (Buses + Regs)
Datapath
Нэгж хугацаанд процессорт
хэрэгжигдэх өгөгдөл түүгээр
дамжих өгөгдөл тэдгээрийн
төлөвт болон үр дүнгийн
элементүүдийн нэгдлийг
өгөгдлийн багц гэнэ.
Register
File
ALU
O/P Reg.
10. Data Path
The data path of a
computer is all the
logic used to process
information
Filled arrow
= info to be processed.
Unfilled arrow
= control signal.
CONTROL
UNIT
11. командууд
•
•
Процессорын үндсэн хэсгийн үйлдлүүд .
бүтэц
– Opcode: operation to be performed
– Operands: data/locations to be used for operation
•
Encoded as a sequence of bits (just like data!)
– Sometimes have a fixed length (e.g., 16 or 32 bits)
– Atomic: operation is either executed completely, or not at all
12. computer science,-m instruction гэдэг нь процессорын нэг үйлдлийг хэлэх
бөгөөд энэ нь командын нэгдсэн бүтцээр тодорхойлогдоно. Өргөн утгаар
тодорхойлбол bytecode бүхий гүйцэтгэгдэх програмын элементүүд бүрийн
тайлбар code. Харин командын нэгдэл нь процессор эсвэл virtual machine,
interpreter зэргийн гүйцэтгэх бүхий л командуудын жагсаалт юм.
Компьютерийн командуудад нь :
• Arithmetic үйлдлийн : add and subtract
• Logic үйлдлийн : and, or, and not
• Өгөгдлийн move, input, output, load, and store
• Control flow буюу хяналтын сигналын goto, if ... goto,
call, and return.
14. • Machine language is built up from discrete
statements or instructions. On the processing
architecture, a given instruction may specify:
• Particular registers for arithmetic, addressing, or
control functions
• Particular memory locations or offsets
• Particular addressing modes used to interpret
the operands
• More complex operations are built up by
combining these simple instructions, which (in a
von Neumann machine) are executed
sequentially, or as otherwise directed by control
flow instructions.
15. • Some operations available in most
instruction sets include:
• moving
• computing
• affecting program flow
16. Some examples of "complex" instructions include:
• saving many registers on the stack at once
• moving large blocks of memory
• complex and/or floating-point arithmetic (sine,
cosine, square root, etc.)
• performing an atomic test-and-set instruction
• instructions that combine ALU with an operand
from memory rather than a register
17. Time to Complete One Instruction
•
Команд тус бүрийн гүйцэтгэлийн сигналын өмнөх болон
хойд фронтын давталтын тоо. It takes fixed number of clock
ticks (repetition of rising or falling edge) to execute each
instruction
Сигнал хоорондын нэг гүйцэтгэлийн үе хоорондыг clock
cycle
Тиймээс командын гүйцэтгэл бүр нэгж clock cycle-р
хэмжигдэнэ
•
нэгж командын сигналын өмнөх фронтын фазын дарааллыг
нэг clock
•
So what determines the time between ticks i.e. the length of the
clock cycle?
18. Clocking Methodology
•
Defines when signals can be read and when they can be written
•
It is important to specify the timing of reads and writes because, if a
value is written at the same time it is read, the value of read could be
old, new or mix of both
•
All values are stored on clock edge (edge-triggered) i.e. within a defined
interval of time (length of the clock cycle)
•
In a processor, since only memory elements can store values this
means that
Any collection of combinational logic must have its inputs coming
from a set of memory elements and its outputs written into a set of
memory elements
19. •
•
The length of the clock cycle is determined as follows:
The time necessary for the signals to reach memory element 2
defines the length of the clock cycle
i.e. minimum clock cycle time must be at least as great as the
maximum propagation delay of the circuit
21. Instruction Processing: FETCH
• Idea
F
– Put next instruction in IR & increment PC D
• Steps
– Load contents of PC into MAR
– Increment PC
– Send “read” signal to memory
– Read contents of MDR, store in IR
EA
OP
EX
S
25. Instruction Processing:
DECODE
• Identify opcode
F
– In LC-3, always first four bits of instruction D
– 4-to-16 decoder asserts control line
EA
corresponding
to desired opcode
OP
• Identify operands from the remaining bits
EX
– Depends on opcode
S
e.g., for LDR, last six bits give offset
e.g., for ADD, last three bits name source
27. Instruction Processing:
EVALUATE ADDRESS
• Compute address
– For loads and stores
– For control-flow instructions
F
D
EA
• Examples
– Add offset to base register (as in LDR)
– Add offset to PC (as in LD and BR)
OP
EX
S
29. Instruction Processing: FETCH
OPERANDS
• Get source operands for operation
F
D
• Examples
– Read data from register file (ADD)
– Load data from memory (LDR)
EA
OP
EX
S
32. Instruction Processing:
EXECUTE
• Actually perform operation
F
D
• Examples
EA
– Send operands to ALU and assert ADD signal
– Do nothing (e.g., for loads and stores)
OP
EX
S
34. Instruction Processing: STORE
• Write results to destination
– Register or memory
• Examples
F
D
EA
– Result of ADD is placed in destination reg.OP
– Result of load instruction placed in destination
EX
reg.
– For store instruction, place data in memory
• Set MDR
• Assert WRITE signal to memory
S
39. Outline of the Book (2)
•
•
•
•
•
•
•
CPU Structure and Function
Reduced Instruction Set Computers
Superscalar Processors
Control Unit Operation
Microprogrammed Control
Multiprocessors and Vector Processing
Digital Logic (Appendix)
40. Internet Resources
- Web site for book
• http://WilliamStallings.com/COA6e.html
– links to sites of interest
– links to sites for courses that use the book
– errata list for book
– information on other books by W. Stallings
• http://WilliamStallings.com/StudentSupport
.html
– Math
– How-to
– Research resources
41. Internet Resources
- Web sites to look for
• WWW Computer Architecture Home Page
• CPU Info Center
• ACM Special Interest Group on Computer
Architecture
• IEEE Technical Committee on Computer
Architecture
• Intel Technology Journal
• Manufacturer’s sites
– Intel, IBM, etc.
42. Internet Resources
- Usenet News Groups
•
•
•
•
comp.arch
comp.arch.arithmetic
comp.arch.storage
comp.parallel
Notas del editor
credential:
bring a computer
die photo
wafer
:
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.
Q: What if we didn’t have MDR/MAR? A: Couldn’t have bus!