1. GOKUL RAMACHANDRAN
440 UNIT-2 GALLERIA DRIVE MOBILE: +1 404-747-6041
SAN JOSE, CA-95134 EMAIL-ID:gokulram1990@gmail.com
SUMMARY
Experienced in RTL verification using System Verilog/UVM in SAT and full chip level test bench. Basic
understanding of all reset methodologies. Knowledge of computer architecture – Processor design. Well
versed in scripting languages like Perl. Hands on experience with Modeling software tools.
EDUCATION
Master of Science, Computer Engineering, University of California- Santa Barbara.
• Cumulative GPA: 3.87/4
• Related coursework: VLSI Testing and Validation, Advanced computer architecture-Distributed
systems, Processor design, VLSI principles, High speed IC design, VLSI project design.
• Date of graduation: March 2014.
Bachelor of Technology(B Tech),Electrical and Electronics Engineering, National Institute of
Technology- Trichy, India
• Cumulative GPA: 8.06/10.
• Related coursework: Circuits and Electronics, Digital integrated circuits, Micro-processors & Micro-
controllers, Object oriented programming, Data structures, Operating systems, Feedback systems and
Analog integrated circuits.
• Date of Graduation: August 2012.
TECHNICAL SKILLSET
• Modeling Software – Synopsys VCS, Verdi, ModelSIM PE, Synopsys PrimeTime, Mentor Graphics
Hspice, Cadence Composer-Schematic, DFT Advisor, Tessent Fastscan, Cadence SOC Encounter
• Programming Languages - C,C++, Verilog, System verilog, UVM, Perl, Python, TCL
• Computer Architecture – Multi Level Cache Operation, Superscalar Instruction Dispatch, Branch prediction,
CPU-GPU interaction, Instruction level Parallelism, Memory consistency Models
• VLSI Design – Digital/Mixed Signal Design, Standard cell based design, Floor planning, DRC, FinFETS,
SRAM design.
WORK EXPERIENCE
Oracle America Inc, Santa Clara, USA April 2014 – present
• Role: Hardware Engineer Team: Globals and DFT verification.
• Topic: Reset Verification.
◦ RTL verification of the Chip power on Reset sequence.
◦ Verification of reset sequence following a fatal error in chip.
◦ Verification of the POR value of SRAM arrays using BIST.
◦ Gained knowledge in basic reset sequence, MBIST and reset through scan architecture.

2. • Topic: Power management
◦ Owned RTL verification of power managenment blocks including Frequecy locked loop clock
generator,Temperature sensor, Power supply calibrator and Voltage droop monitor.
◦ A model of the analog circuits with RTL collar was used to verify the functionality of the blocks.
◦ Developed knowledge in working of a Testbench and its various components to verify a
DUT.
University of California, Santa Barbara,USA September- December 2013
• Role: Teaching Assistant
• Role of Teaching assistant for freshmen level MATLAB course. Handled lab sessions.
ACADEMIC PROJECTS
Project: ECE Department, University of California, Santa Barbara Summer 2013
• Topic: Design of Noc.
• Currently involved in the design of Noc using chisel.
Project: ECE Department, University of California, Santa Barbara Spring 2013
• Topic: Design and testing of Capacitive touch sensor controller
• Involved in the end-to-end design of a sensor controller IC (schematic, layout, floor
planning and fabrication)
Project: ECE Department, University of California, Santa Barbara Winter 2013
• Topic: Design of super scalar instruction dispatch unit.
• Made use of Modelsim to implement an instruction dispatch unit in Verilog, which handles
exceptions using Tomasulo's algorithm.
Project: ECE Department, University of California, Santa Barbara Winter 2013
• Topic: Design of multi - processor cache memory hierarchy using Verilog
• Made use of Modelsim to design a multi-processor cache in Verilog
Project: ECE Department, University of California, Santa Barbara Winter 2013
• Topic: Design of sub-threshold voltage 8T-SRAM using sue,max and Hspice.
• Low power design of 8T SRAM in sub-threshold region and comparison of noise margins with 6T-
SRAM.
Project: ECE Department, University of California, Santa Barbara Fall 2012
• Topic: fault coverage determination in a RISC8 processor using Mentor Graphics tools
of FastScan and DFTAdvisor.
• Calculated fault coverage using design for testability methods , considering stuck at fault and
transition fault models.
Project: Electrical & Electronics Engineering, National Institute of technology,
Trichy, India Jan-May 2012
• Topic: Design of 180nm fully integrated low noise CMOS VCO using cadence.
• Computed the performance parameters like Noise, current consumption, tuning range of the VCO.