Outputs to be stuck in VLSI record for 8th experiment.

1. 8 Bit Adder
module bit_8_adder(A,B,Cin,S,Cout);
input [7:0] A,B;
input Cin;
output [7:0] S;
output Cout;
wire C0,C1,C2,C3,C4,C5,C6;
full_add FA0(A[0],B[0],Cin, S[0], C0);
full_add FA1(A[1],B[1],C0, S[1], C1);
full_add FA2(A[2],B[2],C1, S[2], C2);
full_add FA3(A[3],B[3],C2, S[3], C3);
full_add FA4(A[4],B[4],C3, S[4], C4);
full_add FA5(A[5],B[5],C4, S[5], C5);
full_add FA6(A[6],B[6],C5, S[6], C6);
full_add FA7(A[7],B[7],C6, S[7], Cout);
endmodule
module full_add(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum = a^b^c;
assign carry = (a&b)|(b&c)|(c&a);
endmodule
4 Bit Multiplier
module multiplier_4_bit (A,B,C);
input [3:0] A;
input [3:0] B;
output [7:0] C;
assign C[7:0] =A[3:0] * B[3:0];
endmodule
8 :3 ENCODER
module encoder8_to_3(D0,D1,D2,D3,D4,D5,D6,D7,X,Y,Z);
input D0,D1,D2,D3,D4,D5,D6,D7;
output X,Y,Z;
or (X,D4,D5,D6,D7);
or(Y,D2,D3,D6,D7);
or (Z,D1,D3,D5,D7);
endmodule

2. 3:8 DECODER
module decoder3_to_8(X,Y,Z, D0,D1,D2,D3,D4,D5,D6,D7);
input X,Y,Z;
output D0,D1,D2,D3,D4,D5,D6,D7;
assign D0 = (~X & ~Y&~Z),
D1 = (~X & ~Y&Z ),
D2 = (~X & Y&~Z ),
D3 = (~X & Y&Z ),
D4 = (X & ~Y&~Z ),
D5 = (X & ~Y&Z ),
D6 = (X & Y&~Z ),
D7 = (X &Y&Z );
endmodule
1:8 DEMULTIPLEXER
module demux1_to_8(i,S0,S1,S2, D0,D1,D2,D3,D4,D5,D6,D7);
input I,S0,S1,S2;
output D0,D1,D2,D3,D4,D5,D6,D7;
assign D0 = (i & ~S2 & ~S1 & ~S0),
D1 = (i& ~S2 & ~S1 & S0),
D2 = (i & ~S2 & S1 & ~S0),
D3 = (i & ~S2 & S1 & S0),
D4 = (i & S2 & ~S1 & ~S0),
D5 = (i & S2 & ~S1 & S0),
D6 = (i & S2 & S1 & ~S0),
D7 = (i & S2 & S1 & S0);
endmodule
4:1 MULTIPLEXER
module mux4_to_1(i0,i1,i2,i3,s0,s1,out);
input i0,i1,i2,i3,s0,s1;
output out;
assign out = (i0 & ~s1 & ~s0)|(i1 & ~s1 & s0)|(i2 & s1 & ~s0)|(i3 & s1 & s0);
endmodule

3. 8 BIT ADDER
4 BIT MULTIPLIER
8:3 ENCODER

4. 3:8 DECODER
1:8 DEMULTIPLEXER
4:1 MULTIPLEXER