Analysis and design of ultra low power adc for wireless sensor networks 2

INTERNATIONAL JOURNAL OF ELECTRONICS AND
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 1, January- February (2013), © IAEME
COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 4, Issue 1, January- February (2013), pp. 264-275
IJECET
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ANALYSIS AND DESIGN OF ULTRA LOW POWER ADC FOR
WIRELESS SENSOR NETWORKS

1 2
Sandeep Mehra , CN Khairnar
1
(ECE, JJTU, Jhunjhunu, Rajasthan, India)
2
(FCE, MCTE, Mhow, M.P., India)

ABSTRACT

In the past 10 years, Wireless Sensor Networks (WSN) have grown from a theoretical
concept to a burgeoning modern technology. WSN consists of thousands of cubic millimeter
sized nodes(mote) which have the capability to independently sense, compute and
communicate. These motes are energy autonomous and are deployed in ad-hoc manner at
places where the replacement of batteries is not possible. Because of the small size of the
mote, energy management is a key constraint of the design. Energy consumption must
therefore be minimized in every part of the system. This paper briefly examines every part of
a mote and carries out an in depth study of architectural and circuit design techniques for
ultra low power ADC for maximizing the battery life of a mote and thereby improving
system survivability. We compare various available ADC architectures and propose most
power efficient architecture and specifications for achieving the required ultra-low energy
operation.

Keywords: ADC, Motes, Ultra low power

1. INTRODUCTION

WSNs consists of tens to thousands of distributed motes that sense and process data
and relay it to the end-user. Applications for WSNs range from military target tracking to
industrial monitoring and home environmental control. The distributed nature of micro sensor
networks, capacity of the power source and small size of the mote places an energy constraint
on the sensor nodes and hence energy management is a key constraint of the design. An AA-
sized battery contains roughly 250 µA-years of charge or about 12000J [1]. The average
power consumption of an inch-scale mote, then, must be in the range of tens to hundreds of
microwatts or just a few joules per day. Research into energy scavenging [2][3] suggests that

264

January

micro sensors can utilize energy harvested from the environment. Energy harvesting schemes
convert ambient energy into electrical energy, which is stored and utilized by the node. The
bient
most familiar sources of ambient energy include solar power, thermal gradients, radio radio-
frequency (RF), and mechanical vibration. TABLE1 gives a comparison of power densities of
some energy harvesting technologies [4].
Table 1: Power Densities of Energy Harvesting Mechanisms [4].
Technology Power Density (µW/cm2)
Vibration - electromagnetic 4.0
Vibration - piezoelectric 500
Vibration - electrostatic 3.8
Thermoelectric (50C difference) 60
Solar – direct sunlight 3700
Solar – indoor 3.2

The key challenge of next generation motes is minimizing energy requirement through
aggressive optimization in all layers of design. This paper examines architectural and circuit
design techniques for ADC, which is one critical component of a large scale WSN [5] and
,
propose most power efficient architecture with specifications for WSN. Section 2 describes
typical architecture of a WSN. Sections 2 and 4 examines the architecture and circuit design
of the various ADCs and propose architecture and specifications required for ultra ultra-low
energy operation of ADC finally, Section 5 provides a short conclusion.
2. COMPONENTS OF A WIRELESS SENSOR NODE
WSN are comprised of a number of mm3 sized spatially distributed sensor nodes
which cooperate to monitor the physical qualities of a given environment. A wireless sensor
node is composed of four basic components (Fig.1): a sensing unit, a processing unit
:
(microcontroller), a transceiver unit and a power unit. In the following sub sections we will
an .
explain the hardware components of a sensor mote. Each of the components should be
designed from both operation performance and energy efficiency viewpoint.

Fig.1: Components of a typical Wireless Sensor Node.
omponents

265


2.1 Sensing Unit
A sensor is a device that measures some physical quantity and converts it into a signal
to be processed by the microcontroller. A wide range of sensor types exist including seismic,
thermal, acoustic, visual, infrared and magnetic. Sensors may be passive (sensing without
active manipulation of the environment) or active (using active manipulation/probing of the
environment to sense data, e.g. radar) and may be directional or Omni-directional. TABLE2
lists some common micro-sensors and their main features [6].A wireless sensor node may
include multiple sensors providing complimentary data

Table 2 : Power consumption and capabilities of commonly available Sensors [6]
Sensor Type Current Time Requirement Manufacturer
Photo 1.9 mA 330 µS 2.7 - 5.5V Taos
Temperature 1 mA 400 mS 2.5 - 5.5V Dallas Semiconductor
Humidity 550 µA 300 mS 2.4 - 5.5V Sensiron
Pressure 1 mA 35 Ms 2.2 - 3.6V Intersema
Magnetic Fields 4 mA 30 µS Any Honeywell
Acceleration 2 mA 10 mS 2.5 - 3.3V Analog Devices
Acoustic 0.5 mA 1 mS 2 - 10V Panasonic
Smoke 5 µA -- 6 - 12V Motorola
Passive IR (Motion) 0 mA 1 mS Any Melixis
Photosynthetic Light 0 mA 1 mS Any Li-Cor
Soil Moisture 2 mA 10 mS 2 - 5V Ech2o

The sensing of a physical quantity such as those described typically results in the production
of a continuous analog signal, for this reason, a sensing unit is typically composed of a
number of sensors and an analog to digital convertor (ADC) which digitizes the signal. As
brought earlier ADC is one the major power consuming component of a mote especially in
low power mode. TABLE 3 brings out the average power consumption for the main
components of Micro-LEAP node[7].

Table 3: Average power consumption for the main components of Micro-LEAP node [7]

Active Low-power
Component Power (mW) % Power (mW) %
Processor 2.69 1.95% 2.81 19.93%
Radio 72.74 52.70% 9.40 66.57%
Flash memory 0.029 0.02% 0.027 0.19%
Sensor, MEMS 1.18 0.86% 0.001 0.01%
Sensor, ECG 55.41 40.14% 0.24 1.70%
16-bit ADC 5.97 4.33% 1.64 11.60%
Total 138.04 14.12

2.2 Processing Unit
A microcontroller provides the processing power for, and coordinates the activity of a
mote. Unlike the processing units associated with larger computers, a microcontroller
integrates processing with some memory provision and I/O peripherals; such integration
reduces the need for additional hardware, wiring, energy and circuit board space. In addition
266


to the memory provided by the microcontroller, it is not uncommon for a mote to include some
external memory, for example in the form of flash memory. When we select a commercial
microcontroller family for a WSN application, we need to consider some of the application
requirements including power consumption, voltage requirements, cost, support for peripherals, and
the number of external components required. Some of these are explained in following subsections.

2.2.1 Power consumption
Different microcontrollers have very different power consumption levels. For instance, 8 or
16 bit microcontrollers have varied power consumption between 0.25 to2.5 mA per MHz. Such a
wide difference (over 10 times) between low-power and standard microcontrollers determines the
WSN system performance significantly. The power consumption in sleep mode also varies from 1µA
to 50 µA across various CPUs available which makes considerable difference as the CPU is expected
to be idle for more than 99% of time. Energy consumption in microcontroller also depends on how
much time the operation of entering / exiting sleep mode takes.

2.2.2 CPU speed
In a WSN, the CPU needs to execute the wireless communication protocols and perform local
data processing. Those operations do not need a high-speed CPU. That’s why most of today’s WSN
CPUs have a speed of less than 4MHz. Some WSN CPUs can dynamically change the operating
frequency as per the requirement and reduce power consumption.

2.3 Transceiver
A transceiver unit allows the transmission and reception of data to other devices connecting a
mote to a network. A micro-sensor radio shares the same key design constraints as the other circuit
blocks, including (a) low standby power consumption, (b) fast switching into and out of standby, and
(c) energy efficient operation when active. However, since radios operate at significantly higher
frequencies than the rest of the micro-sensor node and consume milliwatts of power when on, they
have their own specific constraints and limitations and for short range transmission. At GHz
frequencies, the modulator components (frequency synthesizers, mixers, etc.), rather than the power
amplifier, dominate power consumption. Hence, for short packet sizes, the start-up energy
significantly increases the overall transmission energy [4]. Fig.2 illustrates the effect of start-up time
on energy efficiency by plotting the energy to transmit a bit versus packet size. The inefficiency
introduced for short packet sizes can only be improved by reducing the start-up time. Therefore,
implementing an energy efficient transmitter for a micro sensor implies designing a high data rate,
low power, and fast start-up transmitter.

Fig.2: Impact of start-up time on transmitter’s energy consumption[4]

267


2.4 Power Source and its conservation
As an untethered computing platform, mote must be supported by a power unit which
is typically some form of storage (battery). At present there are three common battery
technologies are used in WSNs, i.e., Alkaline, Lithium, and Nickel Metal Hydride. An AA
Alkaline battery is rated at 1.5 V, but during operation it ranges from 1.65 to 0.8 V. With a
volume of 8.5 cm3, it has an energy density of approx 1500 Joules/cm3. While providing a
cheap, high capacity energy source, the major drawbacks of alkaline batteries are the wide
voltage range that must be tolerated and their large physical size. Additionally, lifetimes
beyond 5 years cannot be achieved because of battery self-discharge. In comparison, Lithium
batteries provide an incredibly compact power source. With a volume of 1 cm3, it has and
energy density of 2400 J/cm3. Additionally, they provide a constant voltage supply that
decays little as the battery is drained. One of the drawbacks of lithium batteries is that they
often have very low nominal discharge currents. Nickel Metal Hydride batteries are the third
major battery type. They have the benefit of being easily rechargeable. The downside to
rechargeable batteries is a significant decrease in energy density. An AA size NiMH battery
has approximately half the energy density of an alkaline battery at approximately 5 times the
cost and produce 1.2V. Because many system components require 2.7 volts or more, they it
may not be possible to operate directly off of rechargeable batteries [8]. Fig. 4 illustrates the
battery characteristics for Lithium and Alkaline batteries [8]. The life of power source of a
mote can be increased by power scavenging components (for example, solar cells) and power
conservation techniques such as dynamic voltage scaling. Energy from power scavenging
techniques[2][3] may only be stored in rechargeable (secondary) batteries and this can be a
useful combination in WSN environments where maintenance operations like battery
changing are impractical, such as military and security applications. TABLE4 lists a few
example application domains with an estimate of their deployment lifetimes and computation
requirements [9].

Fig.3: Battery characteristics for Lithium and Alkaline batteries [8].

268


Table 4: Application domains of WSN with an estimate of their deployment
lifetimes and computation requirements [9].

Computation
Desired requirements Example
Application domain
lifetimes (Sample rates)

Scientific applications
• Habitat/weather
Months/decades Very low Great Duck Island
monitoring
• Volcanic eruption
detection Months/decades mid Volcano WSN

Military and security
applications
• Building/border
Years/decades low
intrusion detection
• Structural and
earthquake
Years/decade low/mid
monitoring

• Active battlefield
Sniper
sensing Months Mid/high
detection/localization
Medical applications
• Long-term health
Days low
monitoring (pulse)
• Untethered medical
instruments (ECG) Days Med EKG mote

Business applications
• Supply chain
Months low
management
• Expired/damaged
Months low
goods tracking
• Factory/fab
monitoring Months/years Med/high Industrial WSN

3. ADC ARCHITECTURES AND THEIR APPLICATION AREAS

Depending upon different applications different versions of converter topologies have
come into the world of mixed signal design. Most ADC applications today can be classified
into four broad market segments i.e. data acquisition, precision industrial measurement,
voice-band and audio, and high speed (implying sampling rates greater than about 5MSPS).
A very large percentage of these applications can be filled by successive-approximation

269


register (SAR), sigma-delta (∑−∆), and pipelined ADCs. The successive-approximation ADC
is by far the most popular architecture for data-acquisition applications, while Sigma-Delta
ADC is preferred in precision measurement
And pipelined ADC is chosen for video-audio and high speed applications. The resolution-
speed comparison among the popular ADC architectures along with their primary application
areas is shown in Fig.4 [10].

Fig.4: ADC architectures, applications, resolutions and sampling rates [10].

A comparative study of above listed ADC architectures is presented in following
subsections:-

3.1 Pipelined ADC
A pipelined ADC employs a parallel structure (Fig.5) in which each stage works on
one to a few bits (of successive samples) concurrently. The inherent parallelism increases
throughput, but at the expense of power consumption and latency. Pipelined ADCs frequently
have digital error correction logic to reduce the accuracy requirement of the flash ADCs (i.e.
comparators) in each pipeline stage. A pipelined ADC generally takes up significant silicon
area and for more than 12 bits of accuracy usually requires some form of trimming or
calibration.

Fig.5 : Simplified block diagram of pipelined ADC.

270


3.2 Sigma-Delta ADC
The Sigma-Delta (∑−∆) converter is a primitive, one-bit ADC (Fig.6) operating at a very high
sample rate which averages the results, to obtain a high-resolution result. The digital representation of
the input signal is determined by the percentage of ones in the high-speed bit stream. This is
accomplished by a circuit called a decimation filter to determine the final conversion value. Sigma-
Delta converters have the innate advantage of requiring no special trimming or calibration, even to
attain 16 bits of resolution. But, the process of sampling many times (at least 16 times and often more)
to produce one final sample dictates that the internal analog components in the Sigma-Delta
modulator operate much faster than the final data rate making the architecture more power hungry.
Moreover, the digital decimation filter is also a challenge to design and consumes a significant
amount of silicon area.

Fig.6: Continuous-time 3rd order Σ ∆-modulator block diagram [11].

3.3 Successive Approximation Register (SAR) ADC
SAR ADC is the architecture of choice for nearly all multiplexed data acquisition systems, as
well as many instrumentation applications. The SAR ADC containing an internal DAC, comparator
and a fully digital block, called successive approximation register as shown in Fig.7, is relatively easy
to use, has no pipeline delay, and is available with resolutions up to 18 bits and sampling rates up to 3
MSPS. In summary, the primary advantages of SAR ADCs are low power consumption, high
resolution and accuracy, and a small form factor. Because of these benefits, SAR ADCs can often be
integrated with other larger functions. The main limitations of the SAR architecture are the lower
sampling rates and the requirements for the building blocks (such as the DAC and the comparator) to
be as accurate as the overall system.

Fig.7 : Simplified block diagram of SAR ADC.

271


4. COMPARISON, SELECTION AND SPECIFICATIONS OF SUITABLE ADC
FOR WSN
4.1 Comparison of ADC architecture
When designing ultra-low-power circuits, energy considerations drive the design
process from the choice of architecture all the way to the actual circuit Implementation.
Choosing architecture is a critical point in the design process for such systems. A proper
choice of architecture can lead to dramatic energy savings compared with alternatives.
Conversely, a poor architectural decision can result in a sub-optimal design regardless of how
well the individual circuit blocks are designed. While energy consumption is paramount in
this application space, there are many other considerations driving the choice of ADC
architecture. Fig.8 groups various ADC architectures that vary roughly by their achievable
resolution, speed and power consumption [12]. Since low-power consumption is the primary
design goal, Fig.8 shows that much architectures are poor choices.

Fig.8: Common ADC architectures grouped by resolution, sampling rate and power
consumption [12]
Time interleaved ADCs require multiple sets of analog hardware, leading to high power
consumption but very fast sampling rates. Flash converters use a large number of
comparators for a given resolution, making them impractical in most applications requiring
more than 8 bits of resolution. Folding and/or interpolation can help reduce the number of
comparators required, but the architecture is still not well suited for low-power applications.
Multi-step ADC also requires a relatively large amount of analog hardware, resulting in
excessive power consumption for application in distributed sensor networks. Some of the
other ADC architectures, such as Delta-Sigma, Successive Approximation, Integrating and
Algorithmic, have been reported to work with low-power consumption, low supply voltage
and with moderate resolution and speed [12]. A comparative of reported low power ADCs of
various architectures reported is given at TABLE 5[12][13][14][15]. Oversampled converters
such as sigma-delta converters are potentially viable for this application. Sigma-delta ADCs
can be made to be low-power for a given resolution and sampling rate, however they are
complex, requiring sophisticated clocking and filtering. In addition, the oversampled clock
needs to be much faster than the desired sampling rate. Generating the oversampled clock on
each sensor node would likely offset any energy savings achieved in the rest of the ADC.

272


Table 5 : Summary of performances of some of the reported ADCs of various architectures.
Architecture Technology Supply Sampling Rate Power(µW)
voltage
Delta-Sigma[12] 0.35-µm 1.8 V 1.4 MS/s 108
CMOS
Successive 0.25-µm 1V 100 KS/s 3.1
Approximation[12] CMOS
Successive 0.18-µm 1V 150KS/s 30
Approximation[12] CMOS 0.5 V 4.1 KS/s 0.85
Successive 0.18 µm 1V 12 bit, 100 KS/s 25
Approximation[13] CMOS 12 bit, 500 S/s 200nW
8 bit, 100KS/s 19
Pipeline[14] 0.18-µm 1.8V 16 bit, 125Ms/s 385mW
CMOS
Logarithmic[15] 0.18-µm 1.8V 8 bit, 100KS/s 89-271
CMOS
Integrating[12] 1-µm CMOS 3.3 V -- --
Algorithmic[12] AMS Bi- 2.8 V 2.9 KS/s 8.18 + 9.71
CMOS 2V 0.7 KS/s 1 + 1.3
0.8-µm BYQ

4.2 Selection and specification of suitable ADC
Selection of suitable ADC architecture for a particular system depends on the application.
Low-power sensor networks and biomedical applications often work with low frequency data
which is less than 50 kHz. The TABLE6 [9]lists the range of sampling rates for different physical
phenomena.

Table 6 : Sensor sampling rates of different phenomena[9]..
Phenomena Sample rate (in Hz)
Very low frequency
• Atmospheric temperature 0.017-1
• Barometric pressure 0.017-1

Low frequency
• Heart rate 0.8-3.2
• Volcanic infrasound 20-80
• Natural seismic vibration 0.2-100
Mid frequency (100 Hz – 1000 Hz)
• Earthquake vibrations 100-160 Hz
• ECG (heart electrical activity) 100-250
High frequency (>1 kHz)
• Breathing sounds 100-5 k
• Industrial vibrations 40 k
• Audio (human hearing range) 15-44 k

By studying potential applications for large sensor networks [16], the critical application
constraints were determined to be [5]:

273


• Resolution of 8 to 10 bits;
• Max sampling rate of at least 100 kHz (application dependent);
• Rail-to-rail conversion range—accommodate a variety of
Sensors;
• Algorithmic flexibility—reduced resolution samples, data
thresholding, data binning.

A survey of ADC architectures reveals that both algorithmic and successive approximation
ADCs are well suited to meet the above listed design specifications. These architectures can
be realized using very low power due to the minimal amount of analog hardware required.
However, the successive approximation architecture offers greater flexibility to perform
general operations on the input. Shown in Fig. 7, the successive approximation architecture
uses only one comparator, along with simple digital logic and a switching network to
implement the search algorithm. Assuming a binary search, reduced resolution samples can
be obtained by simply ending the search algorithm early. Thus, an N-bit successive
approximation ADC can produce outputs ranging from 1 to bits of resolution with no circuit
modifications, using less energy for less resolution. While algorithmic ADCs also provide
this feature, the successive approximation architecture offers an additional layer of flexibility
through direct modification of the successive approximation register (SAR) itself. In the
Smart Dust system, the SAR is implemented by a custom microprocessor, and can be
reconfigured easily. For example, the microprocessor (which now acts as the SAR) could
change the search to simply threshold the input, bin the input into an arbitrary number of
bins, or start the search at the value of the last output code. By implementing these SAR
modes with dedicated hardware in the microprocessor, the energy overhead is minimized.
This arbitrary control is programmable by the user at the application level, making the
successive approximation ADC extremely flexible and most suitable for WSN [5][17].

5. CONCLUSION

Designing hardware for WSN requires a holistic approach looking at all areas of the
design space. Researchers all over the world are contributing to improve the life time of
motes employed in WSN. In this paper a comparison of all ADC architectures was done and
SAR ADC has been found to be best suited architecture for WSN. The specifications
including resolution, sampling rate and others of the same has been suggested for design
implementation.

REFERENCES

[1] Ben W. Cook, Steven Lanzisera and Kristofer S. J. Pister, “SoC Issues for RF Smart
Dust,” Proceedings of the IEEE, Vol 94, No. 6, June 2006.
[2] Shad Roundy, Eli S. Leland, Jessy Baker, Eric Carleton, Elizabeth Reilly, Elaine Lai,
Brian Otis, Jan M. Rabaey, V. Sundararajan and Paul K. Wright, "Improving Power Output
for Vibration-Based Energy Scavengers," IEEE Pervasive Computing, vol. 4, no. 1,
pp. 28-36, Jan.-March 2005.
[3] Shad Roundy, Paul K. Wright and Jan Rabaey. "A Study of Low Level Vibrations as
a Power Source for Wireless Sensor Nodes".Computer Communications, vol. 26, no. 11,
2003, pp.1131–1144.

274


[4] B. Calhoun, D. Daly, N. Verma, D. Finchelstein, D. Wentzloff, A. Wang, S. Cho, and A.
Chandrakasan, “Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes,”
IEEE Trans. Computers, vol. 54, no. 6, pp. 727-740, June 2005.
[5] M. D. Scott, B. E. Boser, and K. S. J. Pister, “An ultralow-energy ADC for smart dust,”
IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1123–1129, 2003.
[6] Fei Hu and Xiaojun Cao, wireless sensor networks: principles and practice (Auerbach
Publications,2010).
[7] Lawrence K. Au, Winston H. Wu, Maxim A. Batalin, Dustin H. McIntire and William J.
Kaiser, “MicroLEAP: Energy-aware Wireless Sensor Platform for Biomedical Sensing
Applications,” IEEE Biomedical Circuits and Systems Conference, 2007. BIOCAS 2007, pp. 158
– 162, Nov. 2007.
[8] Jason Lester Hill, “System Architecture for Wireless Sensor Networks,” PhD thesis in
Computer Science in the graduate division of the University of California, Berkeley, Spring 2003.
[9] Mark Hempstead, Michael J. Lyons, David Brooks, and Gu-Yeon Wei, “Survey of
Hardware Systems for Wireless Sensor Networks,” J. Low Power Electronics 2008, Vol. 4, No. 1,
2008.
[10] Walt Kester, “Which ADC architecture Isright for your application,” in [online pdf],
Available: http://www.techdesignforums.com/practice/technique/which-adc-architecture-is-right-
for-your-application/.
[11] J. H. Nielsen, E. Bruun, “A low-power 10-bit continuous-time CMOS Sigma-Delta A/D
converter,” ISCAS Proceedings InternationalSymposium , Vol. 1, May 2004.
[12] AnujAgarwal, “Low-Power Current-Mode ADC for CMOS Sensor IC,” Master’s of
Science thesis in Electrical Engineering in Graduate Studies of Texas A&M University.
[13] N. Verma and A. P. Chandrakasan, “An ultra low energy 12-bit rateresolutionscalable
SAR ADC for wireless sensor nodes,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1196–
1205, Jun. 2007.
[14] Devarajan,S.; Singer, L.; Kelly, D.; Decker, S.; Kamath, A.; Wilkins, P., “A 16b 125MS/s
385mW 78.7dB SNR CMOS pipeline ADC”, Solid-State Circuits Conference -Digest of
Technical Papers, pp: 86, Feb ISSCC 2009.
[15] J. Lee, H.-G. Rhew, D. Kipke, and M. Flynn, “A 64 channel programmable closed-loop
neurostimulator with 8 channel neural amplifier and logarithmic ADC,” IEEE J. Solid-State
Circuits, vol. 45, no. 9, pp. 1935–1945, Sep. 2010.
[16] L. Doherty,B.A. Warneke, B.E.Boser and K.S.J.Pister,”Energy and performance
considerations for Smartdust” International Journal of parallel and distributed systems and
networks, Vol 4, No. 3, 2001.
[17] B.A. Warneke et al., “An autonomous 16 mm3 solar powered node for distributed
wireless sensor networks”, IEEE Sensors 2002 proceedings, vol. 2, p. 1510-1515.
[18] Suhas. S. Khot, Prakash. W. Wani, Mukul. S. Sutaone and Saurabh.K.Bhise, “A 581/781
Msps 3-Bit CMOS Flash ADC Using TIQ Comparator” International journal of Electronics and
Communication Engineering &Technology (IJECET), Volume 3, Issue 2, 2012, pp. 352 - 359,
Published by IAEME.
[19] P.Sreenivasulu, Krishnna veni, Dr. K.Srinivasa Rao and Dr.A.VinayaBabu, “Low Power
Design Techniques of CMOS Digital Circuits” International journal of Electronics and
Communication Engineering &Technology (IJECET), Volume 3, Issue 2, 2012, pp. 199 - 208,
Published by IAEME
[20] S. S. Khot, P. W. Wani, M. S. Sutaone and S.K.Bhise, “A Low Power 2.5 V, 5-Bit, 555-
Mhz Flash ADC In 0.25µ Digital CMOS” International journal of Computer Engineering &
Technology (IJCET), Volume 3, Issue 2, 2012, pp. 533 - 542, Published by IAEME.

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