Split set data weighted averaging – an efficient approach for removal of periodic

International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN
0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 4, Issue 3, April (2013), © IAEME
243
SPLIT SET DATA WEIGHTED AVERAGING – AN EFFICIENT
APPROACH FOR REMOVAL OF PERIODIC NOISE IN DATA
CONVERTERS
Dr. Syed Abdul Sattar1
, Mohammed Arifuddin Sohel 2
Dr. K. Chennakeshava Reddy 3
1
Professor, Royal Institute of Technology and Science, Chevella, Ranga Reddy Dist,
A.P., INDIA
2
Associate Professor, Department of Electronics and Communication Engineering,
Muffakham Jah College of Engineering and Technology, Hyderabad, A.P., India
3
Principal, TKR College of Engineering and Technology, Meerpet, Ranga Reddy Dist,
A.P., INDIA
ABSTRACT
Data Converter (ADC and DAC) architectures which rely on matched components, suffer
performance degradation due to component mismatch. In practice, perfectly matched components like
resistors, capacitor and switches are impossible to fabricate, and mismatch errors are inevitable. These
errors can be corrected by means of Dynamic Element Matching (DEM) techniques. Data Weighted
Averaging (DWA) is the most commonly used DEM technique, but it results in presence of unwanted
inband periodic noise in the output, for a slow varying or DC input. This paper proposes an efficient
technique of mismatch noise shaping, named Split-Set Data-Weighted Averaging (SDWA) that makes
the DAC immune to component mismatch noise and at the same time eliminates the inband noise
tones in the DC response of the System. Hardware implementation of SDWA is cost-effective and
displays low-latency, which makes its use practical, in high speed applications.
Keywords: Data Converters, Component Mismatch, Dynamic Element Matching, Data weighted
averaging, Split Set Data Weighted Averaging.
1. INTRODUCTION
In VLSI circuits, component mismatch errors are caused by process variations such as mask
misalignment, non-uniform oxide thickness, and non-uniform doping densities. Further, mismatch
errors can be generated by temperature gradients across the circuit, component aging and component
noise [1], [2]. In ADCs and DACs, mismatch errors lead to errors in the converter’s transfer function
and thus the converter’s performance is adversely affected.
INTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN
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ISSN 0976 - 6480 (Print)
ISSN 0976 - 6499 (Online)
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244
Various techniques, including special VLSI layout Procedures, Laser Trimming, Self-
Calibration and Dynamic Element Matching (DEM) [3][4][5], can reduce the effects of component
mismatch errors in Data converters that have a resistor based design. While the techniques proposed
in [3][4]and [5] are very costly to implement, the dynamic element matching technique has emerged
as the most efficient cost effective method for reduction of resistor based mismatch errors.
DEM is a dynamic process that reduces the effects of component mismatches in electronic
circuits by rearranging dynamically the interconnections of mismatched components so that the time
averages of the equivalent components at each of the component positions are equal or nearly equal.
By appropriately varying the mismatched components’ virtual positions, the effects of mismatched
components can be reduced, eliminated, or frequency shifted. This technique is known as Data
Weighted Averaging (DWA)[6].
2. COMPONENT MISMATCH PROBLEM IN DAC
A Digital-to-Analog Converter (DAC) is a device that reconstructs a continuous-time analog
signal from its digital form. A unit-element DAC, is a widely used structure for an M-bit DAC, which
is built from unit elements such as resistors or capacitors or current sources. Figure 1 shows the
diagram of the unit-element DAC.
Figure 1 - The Unit-Element DAC
An M-bit unit-element DAC usually has M+1 output levels and for an M-bit input
data, equation 1, describes the output of the unit-element DAC.
(1)
Where is the input data and is the unit-element value. Normal DACs use weighted resistor
technique to implement binary weighted codes. But, the input data to a unit-element DAC, is the
thermometer code in which, the number of 1’s correspond to the decimal value that a code represents.
Table 1 shows the thermometer codes for a seven-level unit-element DAC.

245
Table 1: A 3-Bit Binary to Thermometer Code
Decimal
Binary Thermometer Code
b2 b1 b0 d6 d5 d4 d3 d2 d1 d0
0
1
2
3
4
5
6
7
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0 0 0 0 0
0 0 0 0 0 0 1
0 0 0 0 0 1 1
0 0 0 0 1 1 1
0 0 0 1 1 1 1
0 0 1 1 1 1 1
0 1 1 1 1 1 1
1 1 1 1 1 1 1
A Thermometer based DAC is not a minimal representation, since a binary weighted DAC
requires only N digital inputs and Thermometer based DAC needs 2N
digital input values. This leads
to an additional hardware requirement, of a binary to thermometer code converter. However, a
thermometer based converter does have advantages of low DNL errors, guaranteed monotonicity, and
reduced glitching noise when compared to its binary counterpart [4].
2.1 Thermometer Based DAC
A method to realize a D/A converter with the use of a thermometer code input is to build 2N
-1
equal-sized resistors and switches attached to the virtual ground of an opamp, as shown in figure 2.
Figure 2 - Thermometer Code based Resistor DAC [4]
Many DAC architectures use matched references, amplifiers and switches to perform signal
conversion. DAC references are typically voltages or currents generated by matched components,
such as resistors, transistors, and capacitors. These component values will differ from their design
values due to fabrication process variations and temperature gradients across the circuit. These
variations, or mismatch errors, cause inaccurate output levels such that the DAC’s output contains
harmonic distortion.
2.2 Integral Non Linearity(INL) And Differential Non Linearity(DNL)
The component mismatch problem further leads to non linearity errors called INL and DNL.
INL error is described as the deviation, of an actual transfer function from a straight line joining the
end points of the output. DNL error is defined as the difference between the converter’s ideal code
widths and the converter’s actual code widths. Figure 3 shows the maximum INL and DNL of a non-
ideal three bit DAC.

246
Figure 3: INL and DNL – Nonlinearity for a Three bit DAC [4]
3. DYNAMIC ELEMENT MATCHING
Thermometer codes have a highest priority to select the first unit-element-U0 and lowest
priority to select the last one - U6. Since mismatches usually exist among all the unit elements, the
INL and DNL errors increase in a unit-element DAC by such a selection process. This non linearity
should be reduced in order to achieve high accuracy. A Dynamic Element Matching (DEM) block is
targeted towards reducing this mismatch error.
3.1 Data Weighted Averaging (DWA)
The data weighted averaging DEM algorithm rotates circuit elements at the maximum
possible rate while ensuring that each element is used the same number of times [11]. The circuit
elements are selected sequentially from the array starting with the next available unused element. The
circuit components are used at the maximum possible rate, causing the mismatch errors to sum to zero
more quickly. The output of thermometer DAC with DWA and without DWA, for similar inputs is
shown in Table 2. It is clear that, without DWA U0 is most frequently used unit element and U6 is not
used at all. Comparatively, DWA technique uses all unit elements with equally likely probability and
leads to reduction in mismatch errors.
Table 2: The DWA Encoding
Output without
DWA
Output With DWA
Decimal
input
4 3 1 5 4 3 1 5 0 2 6
Hexdecimal
Output
0f 70 01 3e 0f 70 01 3e 3e 41 7e
U(6) 0 0 0 0 0 1 0 0 0 1 1
U(5) 0 0 0 0 0 1 0 1 1 0 1
U(4) 0 0 0 1 0 1 0 1 1 0 1
U(3) 1 0 0 1 1 0 0 1 1 0 1
U(2) 1 1 0 1 1 0 0 1 1 0 1
U(1) 1 1 0 1 1 0 0 1 1 0 1
U(0) 1 1 1 1 1 0 1 0 0 1 0
3.2 The Inband Noise Tone Generation in DWA algorithm
DWA uses the unit-element cyclically in order to make the long-term average use of each unit
element in the DAC the same. The power spectrum of mismatch errors at DAC output is given by [10]
(2)

247
As can be seen, first-order DAC mismatch errors shaping is achieved by using DWA.
However, if the DAC input is a DC or a low-frequency signal, the mismatch errors are not first-order
shaped [12]. For example, for a six-element DAC with consecutive inputs 2, 2, 2, 2 ,…, the selected
unit elements are going to be (U1 U2), (U3 U4), (U5 U6), (U1 U2) , then the output mismatch errors
are periodic, which results in an undesired situation. With a random input signal, the maximum
achievable resolution of a unit-element DAC with oversampling factor M is given by equation 3.
 (3)
Here, is the variance of the unit elements and N is the number which signifies unit
elements. For a DC input signal to the same unit-element DAC, the spectrum of the mismatch errors
depends on the DC levels [13]. Generally, a low order error component of high power is folded back
into the baseband for some values of DC inputs and the equivalent resolution is then decreased.
In order to overcome the tone problem, a modified algorithm, named split-set data weighted
averaging (SDWA), is proposed. SDWA operates by splitting the unit element set into subsets in a
special way, and randomizing each subset independently.
4. IMPLEMENTATION OF DWA ALGORITHM
DWA employs the technique in which each element of the unit element DAC is not used
again until all the unit elements are used at least once. The algorithm to achieve this is shown below.
4.1 DWA Algorithm
1. Set the pointer to zero level.
2. Convert the input binary data b to thermometer code with n ones starting from t0 to tn.
3. Use the n elements of the DAC from the pointer level.
4. Set the pointer to (n+1) level for the next input.
5. For an N element thermometer DAC with elements starting from 0 to (N-1), if the code
exceeds (N-1) element reuse the elements again starting from 0.
6. Repeat steps 2 to 5 for each input to the DAC.
The above algorithm is implemented in verilog code and when executed in cadence virtuoso
resulted in the test schematic shown in figure 4(a) and its output waveform is shown in figure 4(b).
Figure 4: (a) Test schematic of DWA algorithm (b) output waveform of DWA
The simulation results of DWA algorithm are presented in Table 3, the first element to be
used is U(0), it is not used again until all the other elements U(1) to U(7) are used at least once. For a
binary input 000 to 111, we get the DWA output as 00(h) wherein no elements are one, 01(h) wherein
U(0) is selected, 06(h) wherein the next unused elements U(1) and U(2) are selected, 38(h) in which
elements U(3) U(4) and U(5) are selected and so on. The hexadecimal results 00 01 06 38 79 7e 7f
are in agreement with the cyclic order selection as required by the DWA algorithm.

248
Table 3: Simulation result of DWA algorithm
DWA
input
0 1 2 3 4 5 6 7
DWA
output
00 01 06 38 47 79 7e 7f
U(6) 0 0 0 0 1 1 1 1
U(5) 0 0 0 1 0 1 1 1
U(4) 0 0 0 1 0 1 1 1
U(3) 0 0 0 1 0 1 1 1
U(2) 0 0 1 0 1 0 1 1
U(1) 0 0 1 0 1 0 1 1
U(0) 0 1 0 0 1 1 0 1
The problem with DWA comes when a slow varying signal is given as input. Consider a
binary input 100 given to the DWA block for a series of clock cycles. The result obtained is shown in
Table 4.
Table 4 – Simulation Result of DWA algorithm for constant binary input of 4
DWA
input
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
DWA
output
0f 71 1e 63 3c 47 0f 71 1e 63 3c 47 0f 71 1e 63 3c 47 0f
U(6) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
U(5) 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 0
U(4) 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0
U(3) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
U(2) 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1
U(1) 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1
U(0) 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1
The results obtained are hexadecimal - 0f 71 1e 63 3c 47 78 0f 71 and so on. As can be seen,
the ouput repeats after 7 clock cycles and is an unwanted low frequency noise tone. In-Band tones
generated by the basic DWA algorithm are unacceptable in audio applications[14]. Hence we go for
an improved technique SDWA which is a modification of the basic DWA algorithm.
5. IMPLEMENTATION OF SPLIT-SET DATA WEIGHTED AVERAGING (SDWA)
ALGORITHM
Split set data weighted averaging technique not only performs the cyclic selection as in
DWA, but also rotates the zeroes(0’s) among themselves and ones(1’s) among themselves in every
clock cycle.
5.1 SDWA algorithm
SDWA operates by splitting the unit element set into subsets in a special way, and
randomizing each subset independently. For an N-element DAC, SDWA is carried out in the
following steps:
1. Apply DWA to the N unit elements of the DAC in each clock cycle, i.e., use them consecutively in
a cyclic manner;
2. Split the set of all unit elements into two subsets K and L. Subset K contains elements 1 through k,
where k is the highest unit-element index used; its complement L contains elements with indices k+1
through N;

249
3. Rotate or scramble all elements of K within the subset K , and similarly rearrange the elements of
L internally within the subset L .
4. Return to Step 1, starting with the unit element now occupying position k+1.
It is easy to see that this randomization only minimally disturbs the equal usage of unit elements, and
specifically that all unit elements are used at least M times before any one is used M+1 times. Hence,
the noise floor should not be significantly affected by the process, while the tones are prevented by
the randomization performed in Step 3. The above algorithm is implemented in verilog code and
when executed in cadence virtuoso resulted in the test schematic shown in figure 5(a) and its output
waveform shown in figure 5(b).
(a) (b)
Figure 5: (a) Test schematic of SDWA algorithm (b) Output waveform of SDWA
Consider a seven-level DAC with the input sequence 4, 3, 1, 5. The initial order of the unit elements is
U0, U1, U2, U3, U4, U5, U6. Starting with an input code 4, unit elements U0, U1, U2, and U3 are
used. Then the unit elements are split into two subsets (U0, U1, U2, U3) and (U4,U5, U6), which are
rotated by one position independently in order to give (U3, U0, U1, U2) and (U6, U4, U5). The new
order of all unit elements is thus (U3 U0 U1 U2 U6 U4 U5). A second input data 3 is then going to
choose unit elements (U3 U0 U1). Again the unit elements are split into (U3 U0 U1), (U2 U6 U4 U5)
and are rotated separately. The new order of unit elements now is (U1 U3 U0 U5 U2 U6 U4).The
results of SDWA 00 40 03 1c 71 75 3f and 7f comply with the conditions of DWA circular shift and
split set shifts among zeroes and ones as shown in table 5.
Table 5: Simulation Result of SDWA Algorithm with normal input and DC input of 4
SDWA Input 0 1 2 3 4 5 6 7 4 4 4 4 4 4 4 4
SDWA output
(Hexadecimal)
00 40 03 1c 71 75 3f 7f 78 4B 59 0F 2B 1E 56 3C
U(6) 0 1 0 0 1 1 0 1 1 1 1 0 0 0 1 0
U(5) 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 1
U(4) 0 0 0 1 1 1 1 1 1 0 1 0 0 1 1 1
U(3) 0 0 0 1 0 0 1 1 1 1 1 1 1 1 0 1
U(2) 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 1
U(1) 0 0 1 0 0 0 1 1 0 1 0 1 1 1 1 0
U(0) 0 0 1 0 1 1 1 1 0 1 1 1 1 0 0 0
The advantage of SDWA over DWA comes when a constant input is given to the DAC.
Consider in the following example, wherein, the SDWA block is given input constantly as binary
100(4d) for a series of clock cycles. SDWA eliminates the tones which would have been produced in
case of DWA and the ouput is random without repetition thus eliminating tone problem of DWA.

250
SDWA output 0f 78 4b 59 0f 2b 1e 56 3c depicted in Table 5 shows that there is no repetition
and the tonal problem of DWA is completely eliminated. This happened because of the internal shifts
among the subsets of 0’s and 1’s which result in randomization of the data which was otherwise
periodic and resulted in in-band tones in DWA.
6. CONCLUSION
The output of DWA with binary input 100 was 0f 71 1e 63 3c 47 78 0f and 71 i.e., the pattern
is repeated after every 7 clock cycles, whereas output with binary input 100 when given to SDWA
gives the result 0f 78 4b 59 0f 2b 1e 56 3c. It can be observed that the cyclic repetition pattern is
completely removed. Hence the non-linearity is eliminated. Further, the INL of SDWA is calculated
to be 45 mV and DNL of 25mV which is very low in comparison with standard DWA algorithm.
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