1. Additionneur complet 4 bits AC4
library ieee;
use ieee.std_logic_1164.all;
entity AC4 is
port( A,B: in std_logic_vector(3 downto 0);
som : out std_logic_vector(3 downto 0);
Ret: out std_logic
);
end AC4;
architecture arch of AC4 is
component da is
port ( A,B : in std_logic;
sigma, R : out std_logic
);
end component;
component ac1 is
port ( a,b,r: in std_logic;
S, Ro: out std_logic
);
end component;

2. signal x:std_logic_vector (3 downto 0);
begin
objet1: da port map ( A(0),B(0),som(0),x(0));
objet2: ac1 port map ( A(1),B(1),x(0),som(1),x(1));
objet3: ac1 port map ( A(2),B(2),x(1),som(2),x(2));
objet4: ac1 port map ( A(3),B(3),x(2),som(3),x(3));
Ret<=x(3);
end arch;