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Interna'onal	
  Technology	
  
Roadmap	
  for	
  Semiconductors	
  
Dave	
  Armstrong	
  –	
  Advantest	
  
Ira	
  Feldman	
  –	
  Feldman	
  Engineering	
  
Marc	
  Loranger	
  -­‐	
  FormFactor	
  
	
  
Overview	
  
•  Who	
  are	
  we?	
  
•  Why	
  a	
  roadmap?	
  
•  What	
  is	
  the	
  purpose?	
  
•  Example	
  Trends	
  	
  
•  How	
  can	
  you	
  help?	
  
•  Summary	
  
Armstrong-
Feldman-
Loranger
ITRS	
  Team	
  
•  Three	
  authors	
  of	
  this	
  presenta'on	
  
–  Dave	
  (Advantest)	
  –	
  Test	
  TWG	
  Chairman	
  
–  Marc	
  (FormFactor)	
  -­‐	
  	
  Probing	
  Team	
  Leader	
  
–  Ira	
  (Feldman	
  Engineering)	
  -­‐	
  CommunicaDons	
  
Armstrong-
Feldman-
Loranger
•  Test	
  Working	
  Group	
  
–  More	
  than	
  70	
  professionals	
  
–  More	
  than	
  45	
  companies	
  
•  Large	
  ITRS	
  Team	
  
–  More	
  than	
  a	
  1,000	
  professionals	
  
–  Over	
  100	
  companies	
  
–  16	
  Working	
  Groups	
  
	
  
Why	
  a	
  Roadmap?	
  
•  The	
  ITRS	
  is	
  generated	
  each	
  year	
  to	
  report	
  on	
  the	
  
technological	
  fundamentals	
  of	
  our	
  industry.	
  
•  In	
  addi'on,	
  by	
  extrapola'ng	
  on	
  the	
  trends	
  inherent	
  in	
  
today’s	
  semiconductor	
  technology	
  we	
  iden'fy	
  
disconnects	
  and	
  discuss	
  possible	
  approach	
  to	
  
overcome	
  these	
  challenges.	
  
•  Through	
  this	
  effort	
  we	
  all	
  can	
  get	
  a	
  beOer	
  sense	
  of	
  the	
  
path	
  of	
  least	
  resistance	
  and	
  align	
  our	
  plans	
  and	
  
standards	
  	
  in	
  a	
  fashion	
  which	
  is	
  most	
  likely	
  to	
  succeed.	
  
Armstrong-
Feldman-
Loranger
What	
  Is	
  and	
  What	
  Isn’t	
  the	
  ITRS	
  
Armstrong-
Feldman-
Loranger
What	
  Is	
  the	
  ITRS	
  
–  The	
  combined	
  expert	
  
opinion	
  by	
  this	
  team.	
  
–  The	
  results	
  of	
  many	
  
different	
  technology	
  
models.	
  
–  A	
  “best	
  guess”	
  of	
  where	
  
the	
  industry	
  is	
  heading	
  
for	
  the	
  next	
  15	
  years.	
  
–  A	
  highlighDng	
  of	
  
disconnects	
  and	
  
significant	
  challenges.	
  
What	
  Isn’t	
  the	
  ITRS	
  
–  It	
  doesn’t	
  implement	
  or	
  
define	
  Moore’s	
  Law	
  –	
  it	
  
just	
  tries	
  to	
  predict	
  how	
  
things	
  will	
  likely	
  trend.	
  
–  A	
  commitment	
  from	
  the	
  
involved	
  companies	
  to	
  do	
  
what	
  is	
  reported.	
  
–  Specific	
  soluDons	
  or	
  
prescripDve.	
  
ITRS	
  Process	
  
Armstrong-
Feldman-
Loranger
Working	
  Group	
  
Discusses	
  
Challenges	
  
Sub-­‐Team	
  
Analyzes	
  
Implica'ons	
  
Implica'ons	
  
Discussed	
  with	
  Other	
  
Working	
  Groups	
  
Sub-­‐Team	
  Reconciles	
  
Feedback	
  from	
  Other	
  
Groups	
  
En're	
  Team	
  
Publishes	
  a	
  New	
  
Roadmap	
  Yearly	
  
Test	
  Complexity	
  Drivers	
  
•  Device	
  trends	
  
–  Increasing	
  device	
  interface	
  bandwidth	
  
–  Increasing	
  device	
  integraDon	
  (SoC,	
  SiP,	
  MCP,	
  3D	
  packaging)	
  
•  Homogenous	
  &	
  heterogeneous	
  dies	
  à	
  funcDonal	
  disaggregaDon	
  
–  IntegraDon	
  of	
  emerging	
  and	
  non-­‐digital	
  CMOS	
  technologies	
  	
  
–  Complex	
  package	
  electrical	
  and	
  mechanical	
  characterisDcs	
  
–  Device	
  characterisDcs	
  beyond	
  one	
  sided	
  sDmulus/response	
  
model	
  
–  3	
  Dimensional	
  silicon	
  -­‐	
  mulD-­‐die	
  and	
  MulD-­‐layer	
  	
  
–  IntegraDon	
  of	
  non-­‐electrical	
  devices	
  (opDcal,	
  MEMS,	
  etc.)	
  
–  Fault	
  Tolerant	
  Architectures	
  and	
  Protocols	
  
•  Industry	
  trends	
  
–  450	
  mm	
  wafer	
  transiDon	
  
7
Date	
  =	
  When	
  in	
  Produc'on	
  
Armstrong-
Feldman-
Loranger
ITRS 2013 Overview: Figure 1a A Typical Technology Production “Ramp” Curve (within an established wafer generation)
Wafer	
  Probe	
  Requirements	
  
Parameter	
   MPU	
  &	
  
ASIC	
  
DRAM	
   NAND	
   RF	
  &	
  
AMS	
  
LCD	
  
Drivers	
  
CIS	
  
Wirebond	
  –	
  inline	
  pad	
  pitch	
   X	
   X	
   X	
   X	
   X	
   X	
  
Wirebond	
  –	
  stagger	
  pad	
  pitch	
   X	
   X	
   X	
  
Bump	
  –	
  array	
  pitch	
   X	
   X	
  
I/O	
  Pad	
  Size	
   X	
   X	
   X	
   X	
   X	
  
Wafer	
  Test	
  Frequency	
   X	
   X	
   X	
   X	
  
High	
  Speed	
  I/O	
  Frequency	
   X	
   X	
   X	
  
Wirebond	
  -­‐	
  Probe	
  Tip	
  Diameter	
   X	
   X	
   X	
   X	
   X	
   X	
  
Bump	
  –	
  Probe	
  Tip	
  Diameter	
   X	
   X	
  
Probe	
  Force	
   X	
   X	
   X	
   X	
   X	
  
Probe	
  (AcDve)	
  Area	
  	
   X	
   X	
   X	
   X	
   X	
   X	
  
#	
  of	
  Probes	
  per	
  Touchdown	
   X	
   X	
   X	
   X	
   X	
   X	
  
Maximum	
  Current	
  /	
  Probe	
   X	
   X	
   X	
   X	
   X	
  
Maximum	
  Resistance	
   X	
   X	
   X	
  
Armstrong-
Feldman-
Loranger
Parallelism	
  Trend	
  	
  
Armstrong-
Feldman-
Loranger
SoC	
  (MPU)	
  Bump	
  Pitch	
  Trend	
  
•  Technology	
  shi	
  in	
  2012	
  	
  
Armstrong-
Feldman-
Loranger
Prober	
  accuracy	
  vs.	
  Pad	
  size	
  
•  Prober	
  roadmap	
  is	
  not	
  tracking	
  with	
  decreasing	
  
pad	
  sizes	
  	
  	
  
•  An	
  especially	
  difficult	
  issue	
  for	
  Full	
  Wafer	
  
Contactor	
  probe	
  cards	
  
Armstrong-
Feldman-
Loranger
Next	
  Challenges	
  for	
  Probe	
  Cards	
  
•  Decreasing	
  pad	
  /	
  bump	
  sizes	
  and	
  pitch	
  
•  Increasing	
  parallelism	
  SoC	
  and	
  Memory	
  
•  Increased	
  use	
  of	
  die	
  for	
  MCP,	
  2.5D	
  and	
  3D	
  
integra'on	
  will	
  drive	
  more	
  wafer	
  sort	
  
•  2	
  sided	
  probing	
  
•  Tes'ng	
  stacked	
  devices	
  (e.g.	
  HBM)	
  	
  
•  MEMS	
  and	
  sensor	
  sort	
  test	
  
•  Cost	
  of	
  test	
  as	
  a	
  driver	
  	
  
Armstrong-
Feldman-
Loranger
Opportuni'es	
  for	
  Involvement!	
  
•  Download	
  ITRS	
  data	
  at:	
  
hep://www.itrs.net/Links/2013ITRS/Home2013.htm	
  
•  Provide	
  feedback	
  on	
  test	
  data	
  at:	
  
hep://j.mp/ITRSTestSurvey	
  
	
  
•  Sign	
  up:	
  
	
  dave.armstrong@advantest.com	
  
Armstrong-
Feldman-
Loranger
Summary	
  
•  Great	
  Tool	
  
–  Well	
  accepted	
  independent	
  industry	
  wide	
  reference	
  
•  Challenges	
  
–  Requires	
  broad-­‐based	
  inputs	
  
–  Track	
  potenDal	
  disrupDve	
  technology	
  
•  Help	
  Us	
  	
  
–  Get	
  Involved!	
  
Armstrong-
Feldman-
Loranger

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IEEE Semiconductor Wafer Test Workshop SWTW 2014 - International Technology Roadmap for Semiconductors (ITRS)

  • 1. Interna'onal  Technology   Roadmap  for  Semiconductors   Dave  Armstrong  –  Advantest   Ira  Feldman  –  Feldman  Engineering   Marc  Loranger  -­‐  FormFactor    
  • 2. Overview   •  Who  are  we?   •  Why  a  roadmap?   •  What  is  the  purpose?   •  Example  Trends     •  How  can  you  help?   •  Summary   Armstrong- Feldman- Loranger
  • 3. ITRS  Team   •  Three  authors  of  this  presenta'on   –  Dave  (Advantest)  –  Test  TWG  Chairman   –  Marc  (FormFactor)  -­‐    Probing  Team  Leader   –  Ira  (Feldman  Engineering)  -­‐  CommunicaDons   Armstrong- Feldman- Loranger •  Test  Working  Group   –  More  than  70  professionals   –  More  than  45  companies   •  Large  ITRS  Team   –  More  than  a  1,000  professionals   –  Over  100  companies   –  16  Working  Groups    
  • 4. Why  a  Roadmap?   •  The  ITRS  is  generated  each  year  to  report  on  the   technological  fundamentals  of  our  industry.   •  In  addi'on,  by  extrapola'ng  on  the  trends  inherent  in   today’s  semiconductor  technology  we  iden'fy   disconnects  and  discuss  possible  approach  to   overcome  these  challenges.   •  Through  this  effort  we  all  can  get  a  beOer  sense  of  the   path  of  least  resistance  and  align  our  plans  and   standards    in  a  fashion  which  is  most  likely  to  succeed.   Armstrong- Feldman- Loranger
  • 5. What  Is  and  What  Isn’t  the  ITRS   Armstrong- Feldman- Loranger What  Is  the  ITRS   –  The  combined  expert   opinion  by  this  team.   –  The  results  of  many   different  technology   models.   –  A  “best  guess”  of  where   the  industry  is  heading   for  the  next  15  years.   –  A  highlighDng  of   disconnects  and   significant  challenges.   What  Isn’t  the  ITRS   –  It  doesn’t  implement  or   define  Moore’s  Law  –  it   just  tries  to  predict  how   things  will  likely  trend.   –  A  commitment  from  the   involved  companies  to  do   what  is  reported.   –  Specific  soluDons  or   prescripDve.  
  • 6. ITRS  Process   Armstrong- Feldman- Loranger Working  Group   Discusses   Challenges   Sub-­‐Team   Analyzes   Implica'ons   Implica'ons   Discussed  with  Other   Working  Groups   Sub-­‐Team  Reconciles   Feedback  from  Other   Groups   En're  Team   Publishes  a  New   Roadmap  Yearly  
  • 7. Test  Complexity  Drivers   •  Device  trends   –  Increasing  device  interface  bandwidth   –  Increasing  device  integraDon  (SoC,  SiP,  MCP,  3D  packaging)   •  Homogenous  &  heterogeneous  dies  à  funcDonal  disaggregaDon   –  IntegraDon  of  emerging  and  non-­‐digital  CMOS  technologies     –  Complex  package  electrical  and  mechanical  characterisDcs   –  Device  characterisDcs  beyond  one  sided  sDmulus/response   model   –  3  Dimensional  silicon  -­‐  mulD-­‐die  and  MulD-­‐layer     –  IntegraDon  of  non-­‐electrical  devices  (opDcal,  MEMS,  etc.)   –  Fault  Tolerant  Architectures  and  Protocols   •  Industry  trends   –  450  mm  wafer  transiDon   7
  • 8. Date  =  When  in  Produc'on   Armstrong- Feldman- Loranger ITRS 2013 Overview: Figure 1a A Typical Technology Production “Ramp” Curve (within an established wafer generation)
  • 9. Wafer  Probe  Requirements   Parameter   MPU  &   ASIC   DRAM   NAND   RF  &   AMS   LCD   Drivers   CIS   Wirebond  –  inline  pad  pitch   X   X   X   X   X   X   Wirebond  –  stagger  pad  pitch   X   X   X   Bump  –  array  pitch   X   X   I/O  Pad  Size   X   X   X   X   X   Wafer  Test  Frequency   X   X   X   X   High  Speed  I/O  Frequency   X   X   X   Wirebond  -­‐  Probe  Tip  Diameter   X   X   X   X   X   X   Bump  –  Probe  Tip  Diameter   X   X   Probe  Force   X   X   X   X   X   Probe  (AcDve)  Area     X   X   X   X   X   X   #  of  Probes  per  Touchdown   X   X   X   X   X   X   Maximum  Current  /  Probe   X   X   X   X   X   Maximum  Resistance   X   X   X   Armstrong- Feldman- Loranger
  • 10. Parallelism  Trend     Armstrong- Feldman- Loranger
  • 11. SoC  (MPU)  Bump  Pitch  Trend   •  Technology  shi  in  2012     Armstrong- Feldman- Loranger
  • 12. Prober  accuracy  vs.  Pad  size   •  Prober  roadmap  is  not  tracking  with  decreasing   pad  sizes       •  An  especially  difficult  issue  for  Full  Wafer   Contactor  probe  cards   Armstrong- Feldman- Loranger
  • 13. Next  Challenges  for  Probe  Cards   •  Decreasing  pad  /  bump  sizes  and  pitch   •  Increasing  parallelism  SoC  and  Memory   •  Increased  use  of  die  for  MCP,  2.5D  and  3D   integra'on  will  drive  more  wafer  sort   •  2  sided  probing   •  Tes'ng  stacked  devices  (e.g.  HBM)     •  MEMS  and  sensor  sort  test   •  Cost  of  test  as  a  driver     Armstrong- Feldman- Loranger
  • 14. Opportuni'es  for  Involvement!   •  Download  ITRS  data  at:   hep://www.itrs.net/Links/2013ITRS/Home2013.htm   •  Provide  feedback  on  test  data  at:   hep://j.mp/ITRSTestSurvey     •  Sign  up:    dave.armstrong@advantest.com   Armstrong- Feldman- Loranger
  • 15. Summary   •  Great  Tool   –  Well  accepted  independent  industry  wide  reference   •  Challenges   –  Requires  broad-­‐based  inputs   –  Track  potenDal  disrupDve  technology   •  Help  Us     –  Get  Involved!   Armstrong- Feldman- Loranger