Lessons for MEMS Test Engineers - Ira Feldman 111020

Feldman Engineering

Semiconductor Wafer Test
Technology and Trends:
Lessons for MEMS Test Engineers

Ira Feldman
October 20, 2011

MEMS Testing & Reliability Conference 2011
© 2011 Feldman Engineering Corp.

Outline
}  Market Dynamics
}  Testing Semiconductors vs. MEMS
}  Cost of Test
}  Semiconductor Solutions
}  MEMS Challenges
}  MEMS @ Semiconductor Wafer Test Workshop
}  Conclusion

2

~ 5.5 B Units

“MEMS Roadmap: From Device to Function” Jean-Christophe Eloy, Semicon West 2011 3

DRAM

~ 17.4 B
Units
in 2011

http://www.dramexchange.com/Market/market_activity.aspx 4

Cost of Test – Constant Pressure

“Wafer Level Testing – Challenges and Opportunities” Vikas Sharma, Intel Corporation 5

Package Proliferation

“Backend to the Front Line” William Chen, ASE Group, SWTW 2011 6

Outline
}  Conclusion

7

Device Testing

Device
Stimulus Under Test Response Correct?
(DUT)

8

Traditional Wafer Probe Test Cell

Stimulus

Electrical

DUT
Response

Thermal

Verigy / Advantest 9

Stimulus & Response - Traditional

Electrical
Device
Under Test Electrical
(DUT)
Thermal

•  Semiconductors
•  Oscillators
•  MEMS switches
•  MEMS filters
•  MEMS oscillators

10

Stimulus & Response - Optical

Electrical

Device Electrical
Thermal Under Test
(DUT) Optical
•  Image Sensors
Optical •  LEDs
•  Micro- / Pico -
projectors (DLP,
etc.)
•  Micro bolometers

11

Stimulus & Response – MEMS Sensors

Electrical

Thermal
Electrical
Device
Under Test
Motion
(DUT)
Pressure
•  Accelerometers
Magnetic •  Gyroscopes
•  Magnetic Compass
•  Microphones
•  Speakers
•  Pressure sensors
Pressure …
12

Stimulus & Response – Life Science + ?

Electrical
Electrical
Thermal Device
Under Test Mass
Mass (DUT)
• Valves
•  Pumps
Optical
•  Mixers
Optical •  Micro reactors
•  Sensors
•  Micro explosives
…

Mass include movement of material in / out of DUT such as fluids & gas. 13

Device Testing

Device
Stimulus Under Test Response Correct?
(DUT)

14

Outline
}  Conclusion

15

Cost of Test Drivers

Increasing Tighter
test pad
frequency pitches

Increasing Increasing
transistor probe
count Increased count
Cost

16

Semiconductor Cost - Test Solutions

Test Increased Test Lower
Reduction Parallelism Partitioning Cost

Silicon
Velocity

17

www.bobsspaceracers.com

Confl
Intuit
icting
ive S
olutio
& Cou
ns
nter

18


Semiconductor Cost - Test Solutions

Test Increased Test Lower
Reduction Parallelism Partitioning Cost

Silicon
Velocity

19

Test
Reduction

-  Test Escapes
-  Run time complexity
+  Statistical based sampling
+  Test elimination

20

Increased
Parallelism

-  Increased probe card cost
-  Increased tester resources
+ Decreased handling time
+ Greater prober amortization
+ Reduced floor space
+ Increased Silicon Velocity

21

Test
Partitioning

-  Increased process steps
-  Increased process complexity
+  Optimized high-cost ATE

22

23
“Bemo – Nemo – Remo, The Trifurcation of the ATE Industry”, Jim Healy, Sony LSI Design, ATE Vision July 2011

Outline
}  Conclusion

24

Manual Alignment

www.vortexcontrolsystems.com 25
Electroglas 2001 ca. 1982-5

Technoprobe
Cantilever & Blade

SV Probe

26


ole
eH
cop
ic ros ulus?
l M rical stim
igia n-elect
est r no
V fo
path

Verigy V5400 Testhead 27

Vertical - Buckling Beam

FormFactor: “MEMS for ProbeCard Applications”
Chong Chan Pin – Semicon Singapore 2010

Mann: SWTW Tutorial 2004

SV Probe “Trio”
JEM “VC” 28

Vertical - Buckling Beam

MicroProbe: Apollo Vertical

JEM:VC

SV Probe: Trio
29

MEMS - Vertical

Microfabrica MicroProbe
FormFactor (T1)

MicroProbe (Vx-MP)
30

MEMS - Micro Cantilever

Microfabrica

FormFactor (T3)

MJC (U Probe)
http://www.mjc.co.jp/eng/ir/pdf/MJC070226-s.pdf
JEM
31

Vertical Probe Head

Printed Circuit Board

BGA (Solder Attach)

Space Transformer

Upper Guide
Plate

Spacer

Lower Guide
Plate

MicroProbe Apollo Probes

32

FormFactor CMOS Imaging Solution

Stiffener

PCB

Probe Head

33

Outline
}  Conclusion

34

SWTW 2011

"MSO - Multi-Site Optimizer"
Kevin Fredriken
(SPA GmbH - Germany)

•  MEMS device alternating
rotation across wafer à
required two probe passes.

•  No probe of cap or wafer
exclusion zone

•  Developed four site probe card
and stepping algorithm using
MSO. Inclusive probing with
multi-probes on some die. 35

SWTW 2011

"Probe to Pad Placement Error
Correction for Wafer Level S-
Parameter Measurements"
Steven Ortiz
(Avago Technologies - USA)

•  FBAR structure – resonator plus
cap wafer.Vias through cap wafer
to resonator.

•  Due to very high frequency and
tight specification tolerance, very
sensitive to location of probes
on pad. à Implemented
“calibration” structures to de-
embed the measurements.

36

SWTW 2011

"Ghosting - Touchdown Reduction Using Alternate Site Sharing"
Doron Avidar and Yossi Dadi (Micron - Israel)
When using large multisite arrays that need > 3 touchdowns / wafer, “ghosting” may save
several touchdowns. Examples showed12 to 20% savings. 37

Summary
}  Proven semiconductor cost reduction techniques
}  Not always intuitive
}  Require test engineering
}  Can be applied to MEMS

}  MEMS wafer test challenge
}  Multi-site stimulus and response
}  Proper probe card architectures required
}  Solution integration support

38

Resources
}  IEEE Semiconductor Wafer Test Workshop (SWTW)
}  http://www.swtest.org

}  International SEMATECH Manufacturing Initiative (ISMI)
Probe Card Cost Model
}  http://ismi.sematech.org/modeling/probeCOO.htm

}  SEMI E35-0307
}  Guide to Calculate Cost of Ownership (COO) Metrics for
Semiconductor Manufacturing Equipment

39

Thank You!

Ira Feldman
ira@feldmanengineering.com

Visit my blog
www.hightechbizdev.com
for additional test resources.

40

Lessons for MEMS Test Engineers - Ira Feldman 111020

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