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- 1. Thiết kế nhờ máy tính Nguyễn Thành Kiên Bộ môn Kỹ thuật Máy tính Khoa Công nghệ thông tin, ĐH BKHN
- 13. Quy trình thiết kế mạch dựa trên VHDL
- 15. Một ví dụ VHDL đơn giản
- 16. Một ví dụ VHDL đơn giản
- 18. Code structure library IEEE; use IEEE.std_logic_1164.all; ENTITY full_adder IS PORT (a,b,cin: in bit; s,cout:out bit); END full_adder; Architecture dataflow of full_adder is begin s <= a xor b xor cin; cout <= (a and b) or (a and cin) or (b and cin); end dataflow;
- 29. Ví dụ về ENTITY ENTITY mux IS PORT (a, b: IN std_logic_vector(7 downto 0); sel: IN STD_LOGIC_VECTOR(0 to 1); c: OUT STD_LOGIC_VECTOR(7 downto 0)); END mux;
- 35. library IEEE; use IEEE.std_logic_1164.all; ENTITY adder IS PORT (A,B: IN std_logic_vector(7 downto 0); C: OUT std_logic_vector(7 downto 0)); END adder; Architecture dataflow of adder is begin C <= A+B; end dataflow; Adder A(7:0) B(7:0) C(7:0)
- 39. VD3: asyn-reset DFF & NAND ENTITY example IS PORT ( a, b, clk: IN BIT; q: OUT BIT); END example; --------------------------------------- ARCHITECTURE example OF example IS SIGNAL temp : BIT; BEGIN temp <= a NAND b; PROCESS (clk) BEGIN IF (clk'EVENT AND clk='1') THEN q<=temp; END IF; END PROCESS; END example; --------------------------------------- Sự kết hợp giữa mạch tổ hợp và mạch dãy DEMO
- 40. VD4: Bộ dồn kênh Multilpexor a,b: hai kênh vào 8bit sel: các bit chọn kênh c: kênh ra 8bit
- 57. LIBRARY ieee; USE ieee.std_logic_1164.all; ----------------------------------------- ENTITY mux IS PORT ( a, b, c, d, s0, s1: IN STD_LOGIC; y: OUT STD_LOGIC); END mux; ----------------------------------------- ARCHITECTURE not_ok OF mux IS SIGNAL sel : INTEGER RANGE 0 TO 3; BEGIN PROCESS (a, b, c, d, s0, s1) BEGIN sel <= 0; IF (s0='1') THEN sel <= sel + 1;END IF; IF (s1='1') THEN sel <= sel + 2;END IF; CASE sel IS WHEN 0 => y<=a; WHEN 1 => y<=b; WHEN 2 => y<=c; WHEN 3 => y<=d; END CASE; END PROCESS; END not_ok; LIBRARY ieee; USE ieee.std_logic_1164.all; ----------------------------------------- ENTITY mux IS PORT ( a, b, c, d, s0, s1: IN STD_LOGIC; 7y: OUT STD_LOGIC); END mux; ----------------------------------------- ARCHITECTURE ok OF mux IS BEGIN PROCESS (a, b, c, d, s0, s1) VARIABLE sel : INTEGER RANGE 0 TO 3; BEGIN sel := 0; IF (s0='1') THEN sel := sel + 1; END IF; IF (s1='1') THEN sel := sel + 2; END IF; CASE sel IS WHEN 0 => y<=a; WHEN 1 => y<=b; WHEN 2 => y<=c; WHEN 3 => y<=d; END CASE; END PROCESS; END ok;
- 58. So sánh giữa Signal & Variable
- 61. 3.2. Các kiểu dữ liệu VHDL
- 67. ENTITY traffic_light IS PORT(sensor : IN std_logic; clock : IN std_logic; red_light : OUT std_logic; green_light : OUT std_logic; yellow_light : OUT std_logic); END traffic_light; ------------------------------------------------------------ ARCHITECTURE simple OF traffic_light IS TYPE t_state is (red, green, yellow); Signal present_state, next_state : t_state; BEGIN PROCESS(present_state, sensor) BEGIN CASE present_state IS WHEN green => next_state <= yellow; red_light <= ‘0’; green_light <= ‘1’; yellow_light <= ‘0’; WHEN red => red_light <= ‘1’; green_light <= ‘0’; yellow_light <= ‘0’; IF (sensor = ‘1’) THEN next_state <= green; ELSE next_state <= red; END IF; WHEN yellow => red_light <= ‘0’; green_light <= ‘0’; yellow_light <= ‘1’; next_state <= red; END CASE; END PROCESS; PROCESS BEGIN WAIT UNTIL clock’EVENT and clock=‘1’; present_state <= next_state; END PROCESS; END simple;
- 85. Kiểu bản ghi record TYPE word IS ARRAY(0 TO 3) OF std_logic; TYPE t_word_array IS ARRAY(0 TO 15) OF word; TYPE addr_type IS RECORD source : INTEGER; key : INTEGER; END RECORD; TYPE data_packet IS RECORD addr : addr_type; data : t_word_array; checksum : INTEGER; parity : BOOLEAN; END RECORD; PROCESS(X) VARIABLE packet : data_packet; BEGIN packet.addr.key := 5; --Ok packet.addr := (10, 20); --Ok packet.data(0) := (‘0’, ‘0’, ‘0’, ‘0’); packet.data(10)(4) := ‘1’; --error packet.data(10)(0) := ‘1’; --Ok END PROCESS;
- 90. Các kiểu DL có thể tổng hợp
- 92. Đề tài môn học Thiết kế nhờ MT Nhóm: 6 người/nhóm
Notas del editor
- The initial version of VHDL, designed to IEEE standard 1076-1987, included a wide range of data types, including numerical ( integer and real ), logical ( bit and boolean ), character and time , plus arrays of bit called bit_vector and of character called string . A problem not solved by this edition, however, was &quot;multi-valued logic&quot;, where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE standard 1164 , which defined the 9-value logic types: scalar std_ulogic and its vector version std_ulogic_vector. The second issue of IEEE 1076 , in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to allow ISO-8859-1 printable characters, added the xnor operator, etc. Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in C++) and removed some restrictions from port mapping rules. In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced signed and unsigned types to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known as VHDL-AMS ) provided analog and mixed-signal circuit design extensions. Some other standards support wider use of VHDL, notably VITAL (VHDL Initiative Towards ASIC Libraries) and microwave circuit design extensions. In June 2006, VHDL Technical Committee of Accellera (delegated by IEEE to work on next update of the standard) approved so called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of 'case' and 'generate' statements, incorporation of VHPI (interface to C/C++ languages) and a subset of PSL (Property Specification Language). These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions. In February 2008, Accellera approved VHDL 4.0 also informally known as VHDL 2008, which addressed more than 90 issues discovered during the trial period for version 3.0 and includes enhanced generic types. In 2008, Accellera plans to release VHDL 4.0 to the IEEE for balloting for inclusion in IEEE 1076-2008.
- A very important aspect of a SIGNAL, when used inside a section of sequential code (PROCESS, for example), is that its update is not immediate. In other words, its new value should not be expected to be ready before the conclusion of the corresponding PROCESS, FUNCTION or PROCEDURE.
- Contrary to CONSTANT and SIGNAL, a VARIABLE represents only local infor- mation. It can only be used inside a PROCESS, FUNCTION, or PROCEDURE (that is, in sequential code), and its value can not be passed out directly. On the other hand, its update is immediate, so the new value can be promptly used in the next line of code.
- Constant objects are names assigned to specific values of a type. Constants give the designer the ability to have a better-documented model, and a model that is easy to update. For instance, if a model requires a fixed value in a number of instances, a constant should be used. By using a constant, the designer can change the value of the constant and recompile,
- The encoding of enumerated types is done sequentially and automatically (unless specified otherwise by a user-defined attribute, as will be shown in chapter 4). For example, for the type color above, two bits are necessary (there are four states), being ‘‘00’’ assigned to the first state (red), ‘‘01’’ to the second (green), ‘‘10’’ to the next (blue), and finally ‘‘11’’ to the last state (white).
- Indeed, the pre-defined VHDL data types (seen in section 3.1) include only the scalar (single bit) and vector (one-dimensional array of bits) categories. The pre-defined synthesizable types in each of these categories are the following: Scalars: BIT, STD_LOGIC, STD_ULOGIC, and BOOLEAN. Vectors: BIT_VECTOR, STD_LOGIC_VECTOR, STD_ULOGIC_VECTOR, INTEGER, SIGNED, and UNSIGNED.
- Subtype declarations are used to define subsets of a type. The subset can contain the entire range of the base type but does not necessarily need to. A typical subtype adds a constraint or constraints to an existing type.
- Record types group objects of many types together as a single object. Each element of the record can be accessed by its field name. Record elements can include elements of any type, including arrays and records. The elements of a record can be of the same type or different types. Like arrays, records are used to model abstract data elements.
- Files consist of sequential streams of a particular type. A file whose base object type is INTEGER consists of a sequential stream of integers. This is shown in Figure 4-10.