The document discusses the challenges of validating next generation CPUs. It notes that validation is increasingly critical for product success but requires constant innovation. Design complexity is growing exponentially, requiring up to 70% of resources for functional validation. The number of pre-silicon logic bugs found per generation has also increased significantly. Shorter timelines and cross-site development further complicate the validation process.

1. Validating next generation CPUs Praveen Vishakantaiah President, Intel India Feb 22, 2008 DV Club Bangalore

5. The Pre-Si Verification gap EE Times 03/18/2004 Verification Capabilities is fast becoming the limiting factor for VLSI design improvements EE Times 2004

11. Q&A