AARCH64 VMSA Under Linux Kernel AARCH64 is the 64bit mode for ARMV8. VMSA is the abbreviation of "Virtual Memory System Architecture"

1. AARCH64 VMSA Under Linux Kernel
Haifeng Li
September 26, 2013

2. Outline
1
Physical Memory
2
Virtual Memory Usage in Linux
3
MMU Behavior
Translation Walk
Memory Attributes
4
Summary
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
2 / 20

3. Two points for Physical Memory
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
3 / 20

4. Physical Memory Length&Offset
Three ways to define them in Linux
CONFIG CMDLINE
atags by uBoot
Device tree
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¤
a r c h / arm64 / b o o t / d t s / f o u n d a t i o n −v8 . d t s
...
#a d d r e s s −c e l l s = <2>;
#s i z e −c e l l s = <2>;
...
memory@80000000 {
d e v i c e t y p e = ”memory” ;
r e g = <0x00000000 0 x80000000 0 0 x80000000 >,
<0x00000008 0 x80000000 0 0 x80000000 >;
};
...
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
4 / 20

5. Outline
1
Physical Memory
2
Virtual Memory Usage in Linux
3
MMU Behavior
Translation Walk
Memory Attributes
4
Summary
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
5 / 20

6. Virtual Address Layout in Linux
0xFFFF 8000 0000 0000 − 0xFFFF FFBB FFFE FFFF vmalloc area [∼240GB]
0xFFFF FFBF FBC 0 0000 − 0xFFFF FFBF FBDF FFFF UART [2MB]
0xFFFF FFBF FBE 0 0000 − 0xFFFF FFBF FBE 0 FFFF PCI I/O [64KB]
0xFFFF FFBF FC 00 0000 − 0xFFFF FFBF FFFF FFFF Modules [64MB]
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
6 / 20

7. Outline
1
Physical Memory
2
Virtual Memory Usage in Linux
3
MMU Behavior
Translation Walk
Memory Attributes
4
Summary
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
7 / 20

8. Classic Translation Walk
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
8 / 20

9. ARMV8 page size & Linux Support
ARMV8 supports 4KB, 16KB, 64KB Page size.
Table: Selection Page Size between 4KB & 64KB
4KB
64KB
Software Conf.
Default
TCR EL1.TG1=0b10 & TCR EL1.TG0=0b00
CONFIG ARM64 64K PAGES
TCR EL1.TG1=0b11 & TCR EL1.TG0=0b01
AARCH64 VMSA Under Linux Kernel
*Hardware Conf.
Marvell
September 26, 2013
9 / 20

10. Address Translation (1)
1
AArch64 Linux allows 39-bit (512GB) virtual addresses for
both user and kernel translation.1
2
Which TTBR is used depends only on the VA[63] bit
presented for translation.2
1
2
Documentation/arm64/memory.txt
D5-1711,DDI0487A.a-2
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
10 / 20

11. Address Translation (2)
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
11 / 20

12. Two Descriptors Type
Table Descriptor
BlockPage Descriptor
Block Desc.: First or second Level descriptor,which bit[1] is 0,
gives the base address of a block of memory.
4KB
64KB
Block Size
1GB & 2MB
512MB
Page Desc.: Third descriptor, gives the base address of a
block of memory.
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
12 / 20

13. Table Attributes
Bits[63:59] of descriptor define the attributes for next-level
translation table access.
NSTable[63] Ignored from Non-secure state
APTable[62:61]
APTable[62:61] Effect
00
No effect on permissions in subsequent levels of lookup.
01
Access at EL0 is not permitted.
10
Write access is permitted at any EL.
11
Write access is not permitted at any EL. Read access at EL0 is not neither.
UXNTable[60] Excution Never from EL0
PXNTable[59] Excution Never from EL1
Cache Policies of page table memory is defined by TCR EL1.
¤
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#i f n d e f
/∗ PTWs
#d e f i n e
#e l s e
/∗ PTWs
#d e f i n e
#e n d i f
CONFIG SMP
c a c h e a b l e , i n n e r / o u t e r WBWA n o t s h a r e a b l e ∗/
TCR FLAGS
TCR IRGN WBWA | TCR ORGN WBWA
c a c h e a b l e , i n n e r / o u t e r WBWA s h a r e a b l e ∗/
TCR FLAGS
TCR IRGN WBWA | TCR ORGN WBWA | TCR SHARED
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
13 / 20

14. BlockPage Attributes(1)
UXN,bit[52] Determines whether execution at EL0 of
instructions fetched from the region is permtted.
PXN,bit[51] Determines whether execution at EL1 of
instructions fetched from the region is permtted.
Contiguous, bit[50] A hint bit indicating the translation table
entry is one of a contiguous set of entries. That is, TLB can
cache a single entry to cover the contiguous translation table
entries.
Page Size
4KB
64KB
AARCH64 VMSA Under Linux Kernel
3rd Index Bit Range
0bxxxxx0000
0bxxxxxxxx00000
Marvell
September 26, 2013
14 / 20

15. BlockPage Attributes(2)
nG,bit[11] Determines whether the TLB entry applies to all
ASID values, or only to the current ASID value.nG=0,means
the region is available for all processes.
AF,bit[10] Access flags. 0 indicates a page or block of
memory is accessed for the first time, never hold in TLB, and
an Access flag fault is generated. Linux’s swap usage.
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
15 / 20

16. BlockPage Attributes(3)
SH,bits[9:8] Shareability field.
SH[1:0]
00
01
10
11
Normal Memory
Non-shareable
Unpredictable
Outer Shareable
Inner Shareable
AP[2:1],bits[7:6]
AP[2:1]
00
01
10
11
Access from EL1
Read/write
Read/write
Read-only
Read-only
Access from EL0
None
Read/write
None
Read-only
NS,bit[5] Non-secure bit. For memory access from Non-secure
state, this bit is ignored.
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
16 / 20

17. BlockPage Attributes(4)
AttrIndx[2:0],bits[4:2] Memory Attributes index field, for the MAIR EL1.
Bits of MAIR EL1 encoded as follows.
Encoding
00RW,RW! =00
0100
01RW,RW! =00
10RW
11RW
Meaning
Write-through transient
Non-Cacheable
Write-back transient
Write-through non-transient
Write-back non-transient
Attr<n>[3:0] Meaning
0000
nGnRnE
0100
nGnRE
1000
nGRE
1100
GRE
Linux Support: 0000,0100,1100
R:Read allocate policy – 0(No)1(Yes)
W:Write allocate policy – 0(No)1(Yes)
Transient hint:an access is unlikely to be repeated in future.
Linux Support:0100,1111
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
17 / 20

18. Device Memory Attribute
Gathering
Multiple memory accesses of the same type, read or write, to
the same memory location to be merged into a single
transaction.
Multiple memory accesses of the same type, read or write, to
different memory locations to be merged into a single memory
transaction on an interconnect.
Reordering
The order of transactions is out of program order.
Early Write Acknowledgement
It is a hint to the platform memory system. Assigning the No Early
Write Acknowledgement attribute to a Device memory location
recommends that only the endpoint of the write access returns a
write acknowledgement of the access, and that no earlier point in
the memory system returns a write acknowledge.
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
18 / 20

19. Outline
1
Physical Memory
2
Virtual Memory Usage in Linux
3
MMU Behavior
Translation Walk
Memory Attributes
4
Summary
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
19 / 20

20. Summary
Big changes for VMSA in AARCH64 Linux:
Virtual address & Physical address extend 48bit.
The pagetable is splited into user and kernel.
Page size supported 4KB & 64KB
Introduce new concept for Device Memory.
AARCH64 VMSA Under Linux Kernel
Marvell
September 26, 2013
20 / 20