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1. E2MATRIX
Opp. Phagwara Bus Stand
Parmar Complex, Phagwara
Punjab ( INDIA ).
Contact : +91 9041262727, 9779363902
email : support@e2matrix.com
web : www.e2matrix.com
E2MATRIX
Research Lab
E2MATRIX

2. E2MATRIX
Opposite bus stand parmar complex, Phagwara,Punjab, ( India )
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
support@e2matrix.com, e2matrixphagwara@gmail.com
Sr.No.
Project List (Tanner Eda
tool/cadence virtuoso)
year Publisher
1. 2GHZ PLL Frequency Synthesizer for
Zigbee Applications
2014 International Journal of
Innovative Research in Computer
and Communication Engineering
2. DESIGN AND SIMULATION OF
CMOS OTA WITH 1.0 V, 55db GAIN &
5PF LOAD
2014 International Journal of Managing
Public Sector Information and
Communication Technologies
(IJMPICT)
3. A Novel High Performance Enhanced
Pulse Triggered Flip Flop
2014 International Journal of scientific
research and management
(IJSRM)
4. Implementation of Adiabatic Flip Flop
And Sequential Circuits Based on CPAL
Circuits
2014 International Journal of Advanced
Research in Electrical,
Electronics and Instrumentation
Engineering
5. AN OPTIMAL FLIP FLOP DESIGN
FOR VLSI POWER MINIMIZATION
2014 International Journal of Advances
in Engineering & Technology,
6. VLSI DESIGN OF BARREL SHIFTER
USING COMPLEMENTARY AND
PSEUDO NMOS LOGIC
2014 Proceedings of 4th IRF
International Conference
7. Design of Low Power Combinational
Circuits Using Reversible Logic and
Realization in Quantum Cellular
Automata
2014 International Conference on
Innovations in Engineering and
Technology
8. Performance Analysis of Full Adder
Using Different CMOS Logics
2014 ijesc
9. An Improved Shannon Adder Based Low
Power Bough Wooley multiplier in
Switching Activities of Partial Products
2014 International Journal of
Innovations in Scientific and
Engineering Research (IJISER)
10. Comparative Analysis of low area and
low power D Flip-Flop for Different
Logic Values
2014 International Journal Of
Engineering And Science (IJES)
11. High Performance 8x8 Bit Multiplier
Design Using Pass Transistor Logic
2014 International Journal of Trends in
Computer Science
12. Analysis of Conventional Sram6t at Low
Power and High Performance 32nm
Technologies
2014 Int. Journal of Engineering
Research and Applications
13. ESTIMATION OF STATIC AND
DYNAMIC PARAMETERS OF FLASH
ADC USING 180 NM TECHNOLOGY
2014 IJAICT

3. E2MATRIX
Opposite bus stand parmar complex, Phagwara,Punjab, ( India )
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
support@e2matrix.com, e2matrixphagwara@gmail.com
14. COMPARISON of SRAM CELLS AT
45nm, 32nm and 22nm TECHNOLOGY
2014 Progress In Science and
Engineering Research Journal
15. Compression and Decompression of
Signal Using CMOS Technology...A
Review
2014 International Journal of Advanced
Research in
Computer Science and Software
Engineering
16. Design and Analysis of Multipliers Using
Energy Recovery Adiabatic Logics
2014 International Journal of Emerging
Research in Management
&Technology
17. Design of Moderate Speed and Moderate
Resolution Successive Approximation
Analog to Digital Converter
2014 International Journal of Computer
Science and Mobile Computing
18. Power Efficient CMOS Full Adders with
Reduced
Transistor Count
2014 International Journal of
Engineering Research &
Technology
19. A CMOS BANDGAP AND SUB-
BANDGAP VOLTAGE REFERENCE
CIRCUITS FOR NANOWATT POWER
LSIs
2014 INTERNATIONAL JOURNAL
OF RESEARCH IN COMPUTER
APPLICATIONS AND
ROBOTICS
20. Design of carry look head full adder
using CMOS technique
2014 IOSR Journal of Electronics and
Communication Engineering
21. Comparative Analysis Different Adder
Topologies using 180nm Technology
2014 International Journal for Science
and Emerging Technologies with
Latest Trends”
22. Design of Tunable 3rd Order Chebyshev
Low Pass Filter
based on Floating Inductor
2014 International Journal of Research
in Advent Technology
23. DESIGN OF 4-BIT FLASH ANALOG
TO DIGITAL CONVERTER
USING CMOS COMPARATOR IN
TANNER TOOL
2014 International Journal of Computer
Engineering and Applications
24. DESIGN OF 4-BIT FLASH ANALOG
TO DIGITAL CONVERTER USING
CMOS COMPARATOR IN TANNER
TOOL
2014 KIET International Journal of
Communications & Electronics
25. Design of Low Power Novel Viterbi
Decoder Using Multiple Threshold
CMOS Logic
2014 International Journal of Science
and Research (IJSR)
26. Design and Analysis of 2:1 Multiplexer
Using Low Power Adiabatic Technique
and Its Application in Nibble Multiplexer
2014 International Journal for
Scientific Research &
Development
27. POWER ANALYSIS OF 4T SRAM BY
STACKING TECHNIQUE USING
TANNER TOOL
2014 International Journal of Research
in Engineering and Technology

4. E2MATRIX
Opposite bus stand parmar complex, Phagwara,Punjab, ( India )
+91 90412 – 62727, + 91 97793 – 63902
www.e2matrix.com
support@e2matrix.com, e2matrixphagwara@gmail.com
28. Low Power Design of Standard Digital
Gate Design Using Novel Sleep
Transistor Technique
2014 International OPEN ACCESS
Journal Of Modern Engineering
Research
29. Design and Implementation of Area
Optimized ALU using GDI Technique
2014 INTERNATIONAL
JOURNALOF INNOVATIVE
RESEARCHIN ELECTRICAL,
ELECTRONICS,
INSTRUMENTATION AND
CONTROL ENGINEERING
30. Study and Analysis of Universal Gates
Using Stacking Low Power Technique
2014 International Journal of
Computer Science and
Information Technologies
31. Analysis and Design of High Speed Low
Power Comparator in ADC
2014 International Journal of
Engineering Development and
Research
32. A Novel and High Performance
Implementation of 8x8 Multiplier based
on Vedic Mathematics using 90nm
Hybrid PTL /CMOS Logic
2014 International Journal of Computer
Applications
33. Design and Simulation of Low Power
CMOS Adder Cell at 180nm using
Tanner Tool
2014 International Journal of Computer
Applications
34.
Implementation and Performance
Analysis of a Vedic Multiplier Using
Tanner EDA Tool
2014 International Journal for
Scientific Research &
Development
35. Design and Analysis of Low Power
Multipliers and 4:2 Compressor Using
Adiabatic Logic
2014 International Journal of Emerging
Technology and Advanced
Engineering
36. A TRANSISTOR LEVEL ANALYSIS
FOR A 8-BIT VEDIC
MULTIPLIER
2014 International Journal of
Electronics Signals and Systems