"Limited Patent Technology Overview" Report Sample

Limited Technology Overview
of
US Patent 5662768
Assignee: LSI Logic Corporation
Title: “High surface area trenches for an integrated circuit device”
File date: September 21, 1995
Issue date September 2, 1997
Report Date: June 20, 2010
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This “Sample Report” is not provided for, or intended to be, legal evidence of patent infringement or non-infringement.

Introduction
The following report describes a Limited Technology Overview of LSI Logic’s US patent 5662768. The objective
of this report was to subject the Patent of Interest to a cursory technical review, extract the major technology
features and inventive limitations, and draw preliminary conclusions related to current and future technology
relevance of the invention.
Summary of Results
• Independent claims 15, 24, 27, and 33 appear to be limited to trench capacitors.
• Independent Claims 1 (first) and 20 (second) appear to be the broadest with no trench capacitor limitation.
• Possible product feature applications for the ‘768 include trench capacitors (DRAM and eDRAM), and
possibly interlayer vias, stacked capacitors, bottle-shaped trenches, and isolation trenches.
Summary of Invention
In the ‘768 patent, trenches are etched into a substrate where regions of different chemical composition
extend out from the walls of the substrate and are wider than the opening of the substrate, and where the
substrate can be (but does not have to be) semiconductor and the trench can be (but does not have to be) a
capacitor for a Dynamic RAM memory. Etching of areas defined by lateral impurity region is a major
requirement of some (but not all) claims.

Discussion
Dynamic Random Access Memory (DRAM) and semiconductor technology have continued to evolve at a rapid
pace since the filing date (September 21, 1995) of the ‘768 patent. For this reason and the early file date,
many of the problems posed by the ‘768 invention may have been resolved using a variety of other
techniques. Improvements in lithography techniques, film deposition technology, and development of new
materials has allowed feature sizes and process nodes to evolve to 45nm and below. Atomic layer deposition,
Hi-k dielectric materials, and hemispherical silicon grains (HSG) have allowed for greater trench aspect ratios
and increased capacitor surface area. Highly anisotropic etching trench such as RIE and
deep reactive ion etching (D-RIE), in addition to etch reactors such as inductively coupled plasma (ICP) dry
etching have all contributed to trench designs, bringing trench depth-to-width (aspect) ratios to over 70:1.
Stand-alone DRAM trench designs have lost favor and have been mostly replaced with stacked DRAM
technology. However, bottle-shaped trench technology was still an attractive option for some claims of the
‘768.
While the primary application of the ‘768 invention appears to be focused toward trench capacitors in DRAMs,
the broadly written claims may have some application to other current and future structures such as isolation.
• Independent Claims 1 (first) and 20 (second) appear to be the broadest with no trench capacitor limitation.
Independent claims 15, 24, 27, and 33 appear to be limited to trench capacitors.
• Possible product feature applications for the ‘768 include trench capacitors (DRAM and eDRAM), and
possibly interlayer vias, stacked capacitors, bottle-shaped trenches, and isolation trenches.
• Possible current manufacturers include any stand-alone DRAM or embedded DRAM manufacturers using a
trench capacitors cell design, such as Infineon, Toshiba, Micron Technology, Nanya, TSMC, UMC, IBM.

US Patent# Assignee Title Filed Issued
5662768 LSI Logic
Corporation
High surface area
trenches for an
integrated circuit
device
September 21,
1995
September 2, 1997
Independent
Claims
Dependent Claims Embodiments Patents
Referencing (as of
date of report)
Potential
Technology Level
6 31 4 25 Older, Current, and
Future
Figure 2. Background , key patent areas and conclusions from review
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Background of the Invention Problem the Invention Solves How the Invention Solves the
Problem
The invention relates generally to
methods of forming high-surface
area trenches through a “substrate
having chemically distinct strata” in
silicon wafers during fabrication of
integrated circuits.
At the time of the application, the
available “trench-forming
techniques have not yet proven
able to reliably attain submicron
trenches of the depth to width
ratios necessary to reach the 64
megabit requirements”. (1)
This invention provides a process
for forming trenches having
“nonlinear, high surface-area
sidewalls” that “provide more
capacitance per unit depth than
comparable straight-walled
trenches”.
Figure 1. General invention information.
(1) http://www.google.com/patents/about?id=-tQfAAAAEBAJ&dq=5662768

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Remaining Patent
Life
Typical Analysis
Required to
Illustrate
Structure/Process
Difficulty in
Detecting Key
Patented
Elements
Analysis Limitations General
Analysis
Costs
Limited - Moderate Device cross-
sections and
measurements for
trench. Materials ID
for Impurity regions.
Trench – low
Dimensions – low
Impurity regions -
high
Actual impurities likely
etched away in
processing to final
product so cannot be
detected through
chemical analysis. May be
difficult to prove there
was etching along
boundaries of impurity
regions vs non-impurity
region isotropic etching.
Low
Figure 3. Additional background and key patent areas and conclusions from review.
Embodiments of Invention
The three embodiments included etched trenches with horizontal impurity regions, rounded bottoms, and
integrated circuits containing transistor devices and trench capacitor structures with the inventive features.

Summary and Comparison of Independent Patent Elements
1 15 20 24 27 33
Method of
etching trench
Method of
forming trench
Semiconductor chip Semiconductor
memory chip
Integrated
circuit
Digital system
One or more
impurity
regions
laterally
extending over
a first width
One or more
impurity regions
laterally
extending over a
first width
Semiconductor
substrate
Semiconductor
substrate
Semiconductor
substrate
Plurality of
semiconductor
integrated circuits
incorporating active
devices and trench
capacitors in a
semiconductor
substrate
Etchant access
region
Etchant access
region
-- -- -- --
One or more
trench
sidewalls of
substantially
nonlinear
shape
One or more
trench sidewalls
of substantially
nonlinear shape
Trench with one or
more sidewalls
Trench having one
or more sidewalls
-- --
-- -- Neck region of first
width
Neck region of a
first width
-- --
Figure 4a. Summary and comparison of independent patent elements.

Summary of Independent Patent Elements (continued)
1 15 20 24 27 33
-- -- Body region with at
least one nonlinear
region of a second
width greater than
said first width
Body region of
with at least one
nonlinear region of
a second width
greater than said
first width
-- --
-- -- -- Electrically
Conductive
material interior to
said trench
whereby substrate
and conductive
material form
plates of a trench
capacitor
-- --
-- -- -- -- Plurality of
trench
capacitors with
an insulated
storage plate
Plurality of integrated
circuits each
including a plurality
of trench capacitors
with an insulated
storage plate within
each trench
Figure 4b. Summary and comparison of independent patent elements (continued).

Summary of Independent Patent Elements (continued)
1 15 20 24 27 33
-- -- -- -- Plurality of
active devices in
a circuit
configuration
with at least one
of the trench
capacitors
Plurality of active
devices arranged in a
circuit configuration
with at least one of
the trench capacitors
-- -- -- -- At least some of
the trench
capacitors are in
trenches that
have a neck
region of a first
width
At least some of the
trench capacitors are
in trenches that have
a neck region of a
first width
-- -- -- -- A body region
with at least one
nonlinear region
of a second
width greater
than said first
width
A body region with at
least one nonlinear
region of a second
width greater than
said first width
Figure 4c. Summary of independent patent elements (continued).

"Limited Patent Technology Overview" Report Sample

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"Limited Patent Technology Overview" Report Sample