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Chapter 6

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Qiyo Jung
Qiyo Jung
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William Stallings Computer Organization and Architecture Chapter 6 Input/Output
Input/Output Problems ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Input/Output Module ,[object Object],[object Object],[object Object]
External Devices ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
I/O Module Function ,[object Object],[object Object],[object Object],[object Object],[object Object]
I/O Steps ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
I/O Module Diagram Data Register Status/Control Register External Device Interface Logic External Device Interface Logic Input Output Logic Data Lines Address Lines Data Lines Data Status Control Data Status Control Systems Bus Interface External Device Interface
I/O Module Decisions ,[object Object],[object Object],[object Object],[object Object],[object Object]
Input Output Techniques ,[object Object],[object Object],[object Object]
Programmed I/O ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Programmed I/O - detail ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
I/O Commands ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Addressing I/O Devices ,[object Object],[object Object],[object Object]
I/O Mapping ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Interrupt Driven I/O ,[object Object],[object Object],[object Object]
Interrupt Driven I/O Basic Operation ,[object Object],[object Object],[object Object],[object Object],[object Object]
CPU Viewpoint ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Design Issues ,[object Object],[object Object],[object Object]
Identifying Interrupting Module (1) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Identifying Interrupting Module (2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Multiple Interrupts ,[object Object],[object Object],[object Object]
Example - PC Bus ,[object Object],[object Object],[object Object]
Sequence of Events ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
PC Interrupt Layout 8086 INTR 8259A IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
ISA Bus Interrupt System ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
ISA Interrupt Layout 80x86 INTR 8259A IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 8259A IRQ0 (8) IRQ1 (9) IRQ2 (10) IRQ3 (11) IRQ4 (12) IRQ5 (13) IRQ6 (14) IRQ7 (15) (IRQ 2)
Foreground Reading ,[object Object],[object Object]
Direct Memory Access ,[object Object],[object Object],[object Object],[object Object]
DMA Function ,[object Object],[object Object]
DMA Operation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
DMA Transfer Cycle Stealing ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Aside ,[object Object],[object Object]
DMA Configurations (1) ,[object Object],[object Object],[object Object],[object Object],CPU DMA Controller I/O Device I/O Device Main Memory
DMA Configurations (2) ,[object Object],[object Object],[object Object],[object Object],[object Object],CPU DMA Controller I/O Device I/O Device Main Memory DMA Controller I/O Device
DMA Configurations (3) ,[object Object],[object Object],[object Object],[object Object],[object Object],CPU DMA Controller I/O Device I/O Device Main Memory I/O Device I/O Device
I/O Channels ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Interfacing ,[object Object],[object Object],[object Object],[object Object]
Small Computer Systems Interface (SCSI) ,[object Object],[object Object],[object Object],[object Object],[object Object]
SCSI - 1 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
SCSI - 2 ,[object Object],[object Object],[object Object],[object Object],[object Object]
SCSI Signaling (1) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
SCSI Signaling (2) ,[object Object],[object Object],[object Object],[object Object]
SCSI Bus Phases Arbitration Bus free (Re)Selection Command, Data, Status, Message Reset
SCSI Timing Diagram
Configuring SCSI ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE 1394 FireWire ,[object Object],[object Object],[object Object],[object Object],[object Object]
FireWire Configuration ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
FireWire v SCSI
FireWire 3 Layer Stack ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
FireWire - Physical Layer ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
FireWire - Link Layer ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
FireWire Subactions
Foreground Reading ,[object Object],[object Object]

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Chapter 6

  • 1. William Stallings Computer Organization and Architecture Chapter 6 Input/Output
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  • 7. I/O Module Diagram Data Register Status/Control Register External Device Interface Logic External Device Interface Logic Input Output Logic Data Lines Address Lines Data Lines Data Status Control Data Status Control Systems Bus Interface External Device Interface
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  • 24. PC Interrupt Layout 8086 INTR 8259A IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
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  • 26. ISA Interrupt Layout 80x86 INTR 8259A IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 8259A IRQ0 (8) IRQ1 (9) IRQ2 (10) IRQ3 (11) IRQ4 (12) IRQ5 (13) IRQ6 (14) IRQ7 (15) (IRQ 2)
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  • 43. SCSI Bus Phases Arbitration Bus free (Re)Selection Command, Data, Status, Message Reset
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