Tis PPT contains the Design and Implementation of an Advanced DMA Controller on AMBA-Based SoC

1. Presented By Guided By
RAVITESH BAJPAI Prof. SHIVENDRA SINGH
0111EC07MT09 ASSISTANT PROFESSER
Department of Electronics and
Communication Engineering
Technocrats Institute of
Technology Bhopal M.P
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2. CONTENT
 OBJECTIVE
 ADVANTAGE
 PREREQUESTIES
 LIMITATION
 INTRODUCTION
 FUTURE ENHANCEMENT
 DMA ARCHITECTURE
 SUMMARY
 PERFORMANCE
 CONCLUSION
 CONCLUSION
 REFERENCE
 RESULT
1.
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3. To design and implement an AMBA based advanced DMA controller
which can support hardware triggers, linking operation and channel chaining
transfer.
 provide three dimensions transmission.
which can perform data block moving, data sorting and subframe extraction
of various data structures.
which can completes data transfer of different width of read and write.
which can decrease the power consumption.
Which can achieves AHB bus and APB bus to run in parallel.
Which could adopt buffer and non-buffer data transfer mode
according to the speed of equipments.
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4. WHAT IS SoC ?
WHAT IS DMA ?
WHAT IS AMBA PROTOCOL ?
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5. What is SoC ?
System-on-Chip
Chip +
Software +
Integration =Soc
The SoC chip includes:
-Embedded processo
- ASIC Logics and
analog circuitry
- Embedded memory
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6. What is a DMA
Stands for "Direct Memory
Access.“
DMA is a method of
transferring data from the
computer's RAM to another part
of the computer without
processing it using the CPU
Allows data to be sent directly
from an attached device (such
as a disk drive) to
thememory on the
computer's motherboard.
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7. What is AMBA
(AMBA) =The Advanced Microcontroller
Bus Architecture specification defines an
onchip communications standard for
designing high-performance embedded
microcontrollers.
Three distinct buses are defined within
the AMBA specification:
• the Advanced High-performance
Bus (AHB)
• the Advanced System Bus (ASB)
• the Advanced Peripheral Bus
(APB)
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8. AMBA AHB AMBA ASB AMBA APB
* High performance
* High Performance * Low power
* Pipelined operation
* Pipelined operation * Latched address and control
* Multiple bus masters
* Multiple bus masters * Simple interface
* Burst transfers
* Suitable for many peripherals
* Split transactions
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9. AMBA AHB system
design
• A bus
master is • A bus slave
able to responds to
initiate a read or
read and write
write operation
operations within a
by given
providing AHB AHB address-
an address space range
and control
master slave
informatio
n
AHB AHB
arbiter decoder
• The bus • -The AHB
arbiter decoder is used
ensures that to decode
only one bus address of
master at a each transfer
time is and provide a
allowed to select signal
for the slave
initiate data
transfers.
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10. Timing Diagram of AMBA AHB
Basic transfer Transfer type
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11. Block Diagram of AMBA APB
APB bridge APB slave
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12. Timing Diagram of AMBA APB
Write transfer Read transfer
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13. Interfacing APB to AHB
Read transfers Write transfers
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14. Direct Memory Access controller (DMAC) is an important
component of SoC architecture and Direct Memory Access
(DMA) is an important technique to increase data transfer rate
and MPU (microprocessor unit) efficiency in SoC system.
There are a few of on-chip bus standards, but AMBA Rev
2.0[4] (Advance Microcontroller Bus Architecture) has become
popular industry-standard on-chip bus architecture. The
design of DMAC is compliance to the AMBA specification
for easy integration into SoC.
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15. The connectivity of proposed DMAC architecture
-Uses external memory & memory interface can be used
-APB bridge & System Arbiter will use APB
- DMAC contains AHB slave APB master & APB master
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16. A. Functional Overview
B. Dual-Clock Domain Design
C. Multi-channel Design and Arbitration Mechanism
D. Parameter Sets
E. AHB and APB Operation and Parallelism
F. Asymmetric Asynchronous FIFO Design
G. Interrupt and Error System Design
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17. A. Functional Overview
ARB Master
APB Master
MPU module module
programs asserts bus asserts bus
the request request
parameter signal to get signal to
set access to gain the
the ARB control of
APB after
arbitration
with APB
Parameter
Request and Bridge
sets module
Respond transfer
module parameters
accepts the to AHB
request of Interrupt
Master
data and error
module and
transfer module
APB Master
asserts
interrupt
signal or
Selected error signal
request When data
Requests finds its transfer
enter correspondi completes
arbiter ng or error
module. parameter occurs
set in
parameter
sets module
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18. B. Dual-Clock Domain Design
Advantage of using reduced APB clock
frequency
- Decrease power consumption
- Reduce area design
Use of Pulse synchronous circuit
- To decrease metastability to an
acceptable level
Working of Pulse synchronous circuit
- To synchronized Pulse control signal
transmission between AHB Master and
APB Master, or between interrupt and
Error module and APB Master module
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19. C. Multi-channel Design and Arbitration Mechanism
Multi-channel Design Arbitration Mechanism
ensures the
allow chaining of only one channel has
several transfers access to the bus by
through one transfer observing which
occurrence. channel has the
greatest weight.
The
channel chaining
capability for the The greatest weighted
DMAC allows the
channel will get
completion of a access to the bus,In
DMAC channel hardware channel
transfer to trigger priority
another
DMAC channel
transfer.
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20. D. Parameter Sets
Each parameter set is organized into eight words
(32bit), and for contiguous data transfer, configure
four words, the remaining words use default values
Each parameter set includes source
address,destination address, offset address index
(SRCARY,DSTARY, SRCFRM, DSTFRM), data
width, burst size(ACNT, BCNT, CCNT
control information, such as address
mode, transfer type, data flow control, link
address, chaining transfer control, interrupt and
error masking.
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21. E. AHB and APB Operation and Parallelism
AHB
slave-to-
AHB
AHB Master APB Master
slave
module module
APB AHB
periphera Four slave-to- Between ARB Between ARB
l-to-APB Transfer APB slave and APB slave and APB
periphera type periphera peripheral peripheral
l l
Between
Between FIFO
APB and ARB slave. FIFO and APB
periphera peripheral
l-to-AHB
salve
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22. Data transfer in all four modes
Data transfer in AHB slave-to-AHB slave Data transfer in ARB slave-to-APB
& APB peripheral-to-APB peripheral peripheral APB peripheral-to-ARB slave
 DMAC reads data from AHB  If the APB peripheral is slow
slave for one burst, writing into equipment, user adopt FIFO
FIFO, and asserts request bus buffer by set transfer mode
signal for write operation to register in parameter set, and
meet the requirements of real- the process is like AHB
time. slave-to-AHB slave.
 When one burst data is read  ARB read operation is in parallel
completely and DMAC occupies with APB write
bus again, DMAC writes data to operation, forming a two-stage
ARB slave. pipeline, thus transfer speed is
 Transfer operations carry out in increased greatly
order, until task terminates.
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23. F. Asymmetric Asynchronous FIFO Design
• To reading & writing data width of different
WHY USED size
• for AHB slave to-APB peripheral
WHERE
USED
• for APB peripheral- to AHB slave.
• data buffer in one clock domain.
HOW IT
• In write port, can write and read data
WORKS • In read port, we only read data.
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24. Block Description
DualRAM • It is a 128*32bit
asynchronous dual-port
module SRAM
• Write alignment saves
data when, write data
width < read data width
fifo_align
module • Read alignment saves data
when, write data width >
read data width
• controls reading or writing
fifo_control dual-ram
module • Generates write full signal
and read empty signal
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25. G. Interrupt and Error
System Design
ERROR IN
ERROR IN LINK
FOR INTERRUPT DESIGN PARAMETER
SET
DMAC will generate interrupt SET
signal to MPU
The data transfer Data transfer
request is corresponding to
abandoned. link parameter set is
Data transfer terminates and abandoned.
describe which channel
request is complete.
DMAC will generate
error signal to MPU
and describe which DMAC will generate
channel is error and error signal to MPU
finish the next and describe which
Finish the next channel data channel data link parameter set is
transfer error.
transfer immediately. immediately.
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26. The DMA is designed in Verilog language and successfully
synthesized into the gate-level circuit. The delay of critical path
is 2.45ns, that is, the maximum frequency is 408 MRZ.
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27. Performance Comparision
 No. of Cycles in
this DMA taken in
AN2548 PL081 DMA PDMA PDMA
buffer mode are
DMA (buffer) (non-buffer)
just half to
AN2548 but
greater than than
PL081 AHB to AHB 1920 989 989 -
 For non –
buffer mode this AHB to APB 3072 1320 1564 1012
DMA uses one
third of tatal APB to AHB 3072 1320 1564 1012
cycles of AN2548
& also less than APB to APB 3840 1728 1883 -
PL081.
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28. • AN2548 • PL081 DMA • PROPOSED
DMA DMA
- No busrt
mode - No busrt
-Busrt mode
mode
-No parallel - Parallel
operation -No parallel
operation
operation
-Function of -Function of
APB bridge -Function of
APB bridge
APB bridge
-No non-buffer -No non-buffer
mode -No non-buffer
mode
mode
- Less high - High transfer
transfer rates - High transfer
rates
rates
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29. DMA controls directly data,address
and control signals on APB
It achieves AHB operation and APB
operation run in parallel.
Data transfer mode can be buffer and
non-buffer mode according to practical
application by setting control register.
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30. Metastability could never been avoided in anytime when
transmitting signals between asynchronous clock domains.
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31. Number of hardware & software channels can also
Software channels can also be implemented.
be increased upto two decimals.
Design and Implementation
of an Advanced DMA
Controller on AMBA-Based
SoC
Can also work upon other than 0.18 µm library
Other addressing modes are also possible technology of SMIC.
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32. In the design and implementation of an AMBA based advanced DMA controller .The
DMAC has 6 channels which support hardware triggers, linking operation and channel
chaining transfer to improve the real-time processing capability and provides three
dimensions transmission so as to perform data block moving, data sorting and subframe
extraction of various data structures. Channel arbitration mechanism adopts hardware
priority so that meet the different requirements of fairness and the priority in different
systems and the DMAC supports incrementing and wrapping address modes and
completes data transfer which the data width of read and write is different by
asymmetric asynchronous FIFO. Moreover the DMAC adopts dual-clock domain design
so as to decrease the power consumption.Furthermore the DMAC has the function of
APB Bridge, and it can control address, data and control signals independently and
achieve ARB bus and APB bus to run in parallel. And the DMAC could adopt buffer and
non-buffer data transfer mode according to the speed of equipments. Non-buffer mode
can enhance the data transfer rate significantly.
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33. The performance of our DMAC is better. Each data transfer
rate is increased by about 50%. Between ARB slave and APB
peripheral, this DMA adopts non-buffer mode to transfer
data, and the rate is increased by 67%.If this DMA uses buffer
mode, the performance of PL081 is better than this. But the time
spent more than PL081 is used in signals synchronization. This
DMA adopts dual-clock domain design, and PL081 only has one
clock RCLK. When this DMAC uses non-buffer, even though
signal synchronization will occupy much time, the performance
of this DMA is better than PL081, and the data transfer rate is
increased by 23.3%.And this DMA has more features than
PL081.
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34. Transfer from AHB slave_to AHB master
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35. Transfer from APB Master
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36. Transfer from APB to AHB
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37. Transfer from AHB to APB
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38. Experimental results show that the DMAC has the
advantage of high speed transfer rate and is much
suitable to various application fields, such as
multimedia processing.
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