Adopting capacitive sensing as an interface technology in high-volume, high-visibility applications such as portable media players and mobile handsets has created demand for the same technology in more conventional consumer electronics. This demand has led to significant innovation and several competitive technologies are available. The PSoC architecture allows designers to incorporate multiple capacitive sensing design elements into an application. Buttons, sliders, touchpads, and proximity detectors are supported simultaneously with the same device in the same circuit. Use PSoC to scan capacitive sensors and use the activation status to drive LEDs, control a motor, drive a speaker, and so on. A concept called dynamic reconfiguration allows the CapSense application to use more than 100% of the system resources by reconfiguring as needed on-the-fly. With so many potential applications, design rules must function more as guidelines. This document describes some layout and system design guidelines for PSoC CapSense.

1. Capacitance Sensing—Layout Guidelines
for PSoC CapSense
AN2292
Authors: Mark Lee
Associated Project: No
Associated Part Family: CY8C21x34, CY8C24794
GET FREE SAMPLES HERE
Software Version: None
Associated Application Notes: AN2233a, AN2277, AN2318, AN2403
Application Note Abstract
This application note describes layout guidelines for PSoC® CapSense™.
Figure 1. Application with CapSensePlus—Motor, LED,
Introduction
and Speaker with a Single PSoC
Adopting capacitive sensing as an interface technology in
high-volume, high-visibility applications such as portable
media players and mobile handsets has created demand
for the same technology in more conventional consumer
electronics. This demand has led to significant innovation
and several competitive technologies are available. The
PSoC architecture allows designers to incorporate multiple
capacitive sensing design elements into an application.
Buttons, sliders, touchpads, and proximity detectors are
supported simultaneously with the same device in the
same circuit. Use PSoC to scan capacitive sensors and
use the activation status to drive LEDs, control a motor,
drive a speaker, and so on, as illustrated in Figure 1. A
concept called dynamic reconfiguration allows the
CapSense application to use more than 100% of the
system resources by reconfiguring as needed on-the-fly.
PSoC Placement
With so many potential applications, design rules must
It is good practice to minimize the distance between PSoC
function more as guidelines. This document describes
and the sensors. This is especially true for thin flex
some layout and system design guidelines for PSoC
circuits. The PSoC is usually mounted on the bottom layer
CapSense.
along with other components and the CapSense sensor
pads are placed on the top layer. The PSoC is usually
PCB Guidelines centered relative to the sensors so that the parasitic
capacitance is balanced among the sensors.
In the typical CapSense application, the capacitive
sensors are formed by the traces of a printed circuit board
Board Layers
(PCB) or flex circuit. This section contains PCB guidelines
for CapSense. The most common application involves a two layer board
with sensor pads and hatched ground plane on top and
everything else on the bottom. The two layer stack up is
shown in Figure 2. Four layer boards are used when board
area must be minimized.
January 11, 2008 Document No. 001-41439 Rev. *A 1
[+] Feedback

2. AN2292
Figure 2. Two Layer Stack Up for CapSense Boards Figure 3. Multi Layer Treatment of Sensing and
Communication Lines
COM
COM
Board Thickness
FR4-based designs are found to perform well with B ad G ood
standard board thickness ranging from 0.020quot; (0.5 mm) to
0.063quot; (1.6 mm).
Flex circuits work well with CapSense. All guidelines PSoC Pin Assignment
presented for PCBs also apply to flex. A flex circuit is
An effective method to reduce the interaction between
typically much thinner than a PCB. The flex circuit is
communication and sensor traces is to isolate each by
ideally no thinner than 0.01quot; (0.25 mm). One good feature
port assignment. Figure 4 shows a basic version of this
of flex is the high breakdown voltage provided by the
isolation for a 32-pin QFN package. Because each
Kapton material (290 KV/mm), which provides built in ESD
function is isolated, the PSoC is oriented such that there is
protection for the CapSense sensors.
no crossing for communication and sensing traces.
Trace Length and Width Figure 4. Port Isolation for Communication and Sensing
The parasitic capacitance of the traces and sensor pad is T o S ensors
minimized to make the dynamic range of the system as
large as possible. Trace capacitance is minimized by short
and narrow traces. Traces must be less than 12quot; (300
mm) for a standard PCB and less than 2quot; (50 mm) on flex
To Sensors
To Sensors
circuits.
Trace width also plays a role in the parasitic capacitance.
Decreasing the trace width decreases the parasitic
capacitance. Trace widths of 0.0065quot;–0.008quot; (0.17–0.20
mm) suffice for most applications.
Trace Routing T o C om m unication
Route sensor traces on the bottom layer of the PCB. With
Vias
this approach to routing, the only user interaction with the
CapSense sensors is with the active sensing area and not Use the minimum number of vias consistent with routing of
with the traces to the sensor. Do not route traces directly the CapSense inputs to minimize parasitic capacitance.
under any sensor pad unless the trace is connected to that The placement of the via is done anywhere on the sensor
sensor. pad, as shown in Figure 5.
Do not run capacitive sensing traces in close proximity Figure 5. Via to Sensor Pad is Anywhere on the Pad
with and parallel to high frequency communication lines, (Trace on Bottom Layer, Sensor Pad on Top Layer)
such as an I2C or SPI master. If it is necessary to cross
communication lines with sensor pins, make sure the
intersection is at right angles, as illustrated in Figure 3.
January 11, 2008 Document No. 001-41439 Rev. *A 2
[+] Feedback

3. AN2292
ground fill area separates the traces of each button group.
Ground Plane This prevents coupling between the independent
Ground fill is added to both the top and bottom of the CapSense groups.
sensing board. When ground fill is added near a
CapSense sensor pad, there is a tradeoff between
Buttons
maintaining a high level of CapSense signal and
increasing noise immunity of the system. Typical hatching A button determines the presence or absence of a
for the ground fill is 15% on the top layer (7 mil line, 45 mil conductive object. A typical application of a CapSense
spacing) and 10% on the bottom layer (7 mil line, 70 mil button is to sense the presence of a finger.
spacing), as shown in Figure 6.
Sensor Shape
Figure 6. Partial Ground Fill to Minimize Parasitic
The recommended shape for sensing a finger press is a
Capacitance
solid round pattern as shown in Figure 7.
Figure 7. Large Button with Ground Plane
The Buttons section discusses how the clearance between
the sensor pad and ground affects capacitance and
sensitivity.
Other Board Considerations
Programming Pins
Sensing lines in capacitive sensing applications must be
Figure 8 shows the shape recommendations for buttons. A
connected to sensors only. Sensing lines that are attached
square or rectangular button works if the layout does not
to other board elements, such as ISSP programming
support a round shape. Buttons should not be triangular or
headers, are more sensitive to external noise and have a
include other pointed features with angles less than 90
higher parasitic capacitance due to increased surface area
degrees. Interdigitated sensor traces do not work well for
of the conductive path. Avoid placing sensors on the
CapSense buttons implemented with the CSD and CSA
programming pins, P1[0] and P1[1].
sensing methods.
EMC
Figure 8. Shape Recommendations for Buttons.
Resistors placed in series with the CapSense input
dampen the resonance of each trace. This is an effective
way to increase the RF immunity of the system. These
series resistors must be placed close to the PSoC to be
effective against RF interference. The recommended
series resistance added to the CapSense inputs is 560
ohms. Communication lines, I2C, and SPI, also benefit
from series resistance. 300 ohms is the recommended
series resistance for communication lines.
CapSense sensors and their associated traces are
Sensor Size
isolated from other circuit elements. This is especially true
of antennae and other signal sending and receiving All things being equal, larger buttons are typically better.
elements. Refer to application note AN2318, EMC Design Two buttons connected to the PSoC with identical traces
Considerations for PSoC CapSense(TM) Applications for have different sensitivities if they are different in size.
information on this topic.
Clearance Between Sensor and Ground
LED Backlighting
The ground plane is placed on the same layer of the board
CapSense works well with LED backlighting. Cut a hole in
as the buttons as shown in Figure 7. The clearance
the sensor pad; keep LED traces on the bottom layer of
between the button and ground plane plays an important
the board.
role in the performance of the button. Electric field lines
Multiple PSoCs on One PCB fringing between a button and the ground plane are
illustrated in Figure 9. The parasitic capacitance of the
For systems with many buttons, such as a keyboard, the
sensor, Cp, is related to this electric field.
system design may require two or more PSoCs dedicated
to CapSense. In this case, partition buttons so that a
January 11, 2008 Document No. 001-41439 Rev. *A 3
[+] Feedback

4. AN2292
Figure 9. Button-Ground Plane Fringing Fields Figure 11. Sensor Capacitance, Csensor, as a Function of
Button-Ground Clearance and Button Diameter
B utton
G round G round
The capacitance Cp decreases as the clearance
surrounding the button is increased. An example of this
dependence of Cp on the gap is shown in Figure 10
through Figure 13. In these plots, the board material is
FR4 with a thickness of 62 mils (1.57 mm), and the acrylic
overlay has a thickness of 2 mm. Each plot contains data
for three button sizes (5 mm, 10 mm, and 15 mm
diameter).
The Cp in Figure 10 does not include the effect of the
traces or vias. It is only the parasitic capacitance of the
sensor pad itself.
Figure 10. Parasitic Capacitance, Cp, as a Function of
Button-Ground Clearance and Button Diameter
Note The finger is not on the sensor. Sensor capacitance
decreases with the size of the gap.
The capacitance Cf in Figure 12 is the capacitance added
by the touch of the finger. Total capacitance of the sensor
pad and the finger is Cp + Cf.
Figure 12. Finger Capacitance, Cf, as a Function of
Button-Ground Clearance and Button Diameter.
Note The finger is not on the sensor. Capacitance
increases with sensor size, but decreases with the gap.
The capacitance Csensor is the total sensor capacitance
when the finger is not on the sensor. It includes the effect
of the sensor pad, the traces, and vias. Figure 11 shows
the sensor capacitance for a board routed with 50 mm
trace length, 8 mil (0.3 mm) trace width, and 20 mil (0.8
mm) spacing from trace to the co-planar ground.
Note The finger is on the sensor. Capacitance increases
with both sensor size and gap.
January 11, 2008 Document No. 001-41439 Rev. *A 4
[+] Feedback

5. AN2292
Figure 13 plots finger capacitance as a percentage of the Slider Segment Size and Spacing
sensor capacitance. This is the sensitivity of the sensor.
When the finger is placed on the slider, a signal must be
The sensitivity of the system changes with the routing of
produced on at least three adjacent sensor segments for
the CapSense traces. For example, increasing the trace
proper operation of the centroid algorithm. This guides the
length between the PSoC and the sensor pad decreases
sizing of the slider segments. The jagged edges of the
the button’s sensitivity.
slider pattern enable more segments to be active at each
finger location along the slider.
Figure 13. Sensitivity, Cf,/Csensor as a Function of Button-
Ground Clearance and Button Diameter
As with buttons, the total surface area of each slider
element influences the signal. Bigger slider segments lead
to a higher signal level.
The same guidelines given for button to ground clearance
apply to sliders. Slider segments are scanned one at a
time, with all other CapSense inputs grounded.
Neighboring segments present ground to the segment
being scanned, so the segment to segment gap must be
the same as the gap from segment to ground.
Figure 14. CapSense Slider
Note The sensitivity increases with both button size and
gap.
The CapSense signal results from converting the sensor
capacitance changes into digital count values. How large
should the signal be? This depends on the noise in the
system. The signal and noise levels both vary with the
operating point established by firmware parameters. What
is important for proper performance of a CapSense button
is a large Signal-to-Noise ratio (SNR). The minimum Slider Diplexing
recommended SNR for CapSense buttons is 5:1. Refer to
If IO pins are at a premium, connecting two slider
application note AN2403, Signal-to-Noise Ratio
elements to a single PSoC pin increases the number of
Requirement for CapSense Applications for more details
slider elements that are sensed by the PSoC (and thus the
on CapSense SNR.
linear distance) two-fold. This technique is called
diplexing. This option is selected in the User Module
Sliders Wizard. However, the pin assignment for elements in the
slider is prescribed by a diplexing table. An example of a
Sliders are used for controls requiring gradual
diplexed slider with 12 slider elements (6 PSoC input pins)
adjustments. Examples include a lighting control (dimmer),
is shown in Figure 15.
volume control, and speed control. The CapSense
sensors in a slider are mechanically adjacent to one Figure 15. Diplexed Slider Basic Example (Six Pins)
another. Actuation of one sensor results in partial
actuation of physically adjacent sensors. The actual
position in the slider is found by computing the centroid
location of the set of activated sensors as shown in Figure
14. The practical lower limit number for sensor sliders is
five. The upper limit is the number of sensor pins available
on the selected PSoC device.
0 1 2 3 4 5 0 3 1 4 2 5
Large parasitic capacitance is a negative feature of
diplexing. The parasitic capacitance approximately
doubles with diplexing and this technique is not
recommended for use with thick overlays.
January 11, 2008 Document No. 001-41439 Rev. *A 5
[+] Feedback

6. AN2292
Table 1 shows some basic diplexing tables. Touchpads
Table 1. Common Diplexing Tables The CapSense User Module does not directly support
touchpads. Touchpads are implemented as two
6 Pins, 8 Pins, 10 Pins,
independent sliders. All guidelines for sliders also apply to
12 Elements 16 Elements 20 Elements
touchpads.
0 0 0
Figure 18. Touchpads Use Two CapSense Sliders (for X
1 1 1
and Y)
2 2 2
3 3 3
4 4 4
5 5 5
0 6 6
3 7 7
1 0 8
4 3 9
2 6 0
5 1 3
4 6
Touchpad Resolution
7 9
An example of a commercially successful CapSense
2 1
touchpad design implements a 20 position column slider
5 4 (X) and a 10 position row slider (Y). A total of 30 pins are
assigned as CapSense inputs. The dimensions of the
7
active area are 3.9quot; x 1.9quot; (99 mm x 47 mm). The overlay
2
is 0.010quot; (0.25 mm) ABS plastic. The row and column
5 sensors are spaced with a pitch of 0.2quot; (5 mm). The
baseline noise level is a single count in the finger-absent
8
state. A finger on the touchpad produces a difference
Figure 16. Diplex Slider Data from Finger Press on Left signal of 15 counts, which results in an SNR of 15:1.
Side of Slider Setting the centroid algorithm to resolve 20 positions
between each row pair and each column pair, this
touchpad system has a resolution of 100 counts per inch.
Touchpad Layout Patterns
The CapSense User Module does not directly support
touchpads. Touchpads are implemented as two
independent sliders. All the guidelines that apply to sliders
also apply to touchpads.
Two example touchpad layouts are shown in Figure 19
and Figure 20.
Figure 17. Diplex Slider Data from Finger Press on Right
Side of Slider
Figure 16 and Figure 17 represent the data collected by
the PSoC relative to finger position. The User Module
firmware determines finger position by analyzing the
pattern of the signals in the slider array.
January 11, 2008 Document No. 001-41439 Rev. *A 6
[+] Feedback

7. AN2292
Figure 19. Hexagon Touchpad Layout The geometry of this simple system is captured in the ratio
A/d. A is the area of the conductive plates, d is the
distance between the plates, r is the dielectric constant
Y1 (permittivity) of the material between the sensors, and 0 is
the permittivity of free space.
Y2
Y3 The geometry of the CapSense system is more complex
than the parallel plate capacitor. The conductors in the
Y4 sensor include the finger and PCB copper. In general, the
Y5 geometry of this capacitive system is captured by the
function f(A,d). Equation 2 states the relation between
geometry, the dielectric constant, and the system
X1 X2 X3 capacitance.
C   r  0 f ( A, d ) Equation 2
Figure 20. Octagon Touchpad Layout Similar to the parallel plate capacitor, the finger
capacitance of the sensor is directly proportional to r.
High dielectric constants lead to high sensitivity. Air has
the lowest dielectric constant, and any air gaps between
the sensor pad and overlay must be eliminated.
Y1
Dielectric constants of some common overlay materials
Y2 are listed in Table 2. Materials with dielectrics between 2.0
and 8.0 are well suited to capacitive sensing applications.
Sensing through a metal surface is challenging and is not
Y3
recommended.
X1 X2 X3 Table 2. Dielectric Constants of Common Materials
r
In both layouts and for touchpads in general, it is good Material
practice to surround the touchpad with a ground plane that
Air 1.0
follows the contours of the sensing elements.
Formica 4.6–4.9
Proximity Sensors Glass (Standard) 7.6–8.0
Glass (Ceramic) 6.0
A proximity sensor is implemented as a CapSense button
with large CP and small difference counts. A dedicated PET Film (Mylar®) 3.2
proximity sensor is best implemented as a single length of Polycarbonate (Lexan®) 2.9–3.0
wire. Connecting button and slider sensors already on the
Acrylic (Plexiglass®) 2.8
CapSense PCB into a single large sensor is another
technique of implementing a proximity sensor. CSD is the ABS 2.4–4.1
best method to use for proximity sensing. CSD performs Wood Table and Desktop 1.2–2.5
better than CSA with large CP values and the shield
Gypsum (Drywall) 2.5–6.0
feature of CSD is used to extend the detection distance of
the sense wire.
Protective Overlay
An overlay is the covering that is placed over the sensor
pads of the sensor PCB. The overlay material and
thickness are both important design considerations.
Overlay Material
The influence of the dielectric properties of the overlay
material on system performance is understood by
considering a simple parallel plate capacitor. The
capacitance of a parallel plate capacitor is given in
Equation 1.
 r 0 A
C Equation 1
d
January 11, 2008 Document No. 001-41439 Rev. *A 7
[+] Feedback

8. AN2292
Table 3. Maximum Overlay Thickness with a Plastic
Overlay Thickness Overlay Material
Sensitivity is inversely proportional to overlay thickness, as

illustrated in Figure 21. Refer to the Buttons section of this Design Element
document for a specific example of this characteristic. Button <5 mm
Figure 21. Sensitivity vs.Overlay Thickness Slider <2 mm
Touchpad <0.5 mm
The overlay must be thick enough to prevent dielectric
breakdown due to electrostatic voltage on the human
body. Table 4 shows the minimum overlay thickness
required to withstand 12 KV for common overlay materials.
The overlay in the CapSense system protects the PSoC
from permanent damage when the thickness guidelines of
the table are followed. A layer of Kapton tape works well in
applications requiring extra ESD protection.
Table 4. Breakdown Voltage of Overlay Materials and
Minimum Thickness to Prevent Breakdown
Minimum Overlay
Breakdown
Material Thickness at
Voltage [V/mm]
12 KV [mm]
Air 1200–2800 10
Glass–Common 7900 1.5
Both signal and noise are affected by the overlay
properties. As thickness of the overlay increases, signal Glass–Borosilicate 13,000 0.9
and noise both decrease. A representative plot of (Pyrex)
CapSense signal versus overlay thickness is shown in Formica 18,000 0.7
Figure 22.
ABS 16,000 0.8
Figure 22. Signal Level Drops as Overlay Thickness Acrylic 13,000 0.9
Increases (Plexiglass®)
Polycarbonate 16,000 0.8
(Lexan®)
PET Film (Mylar®) 280,000 0.04
Polyimide Film 290,000 0.04
(Kapton®)
FR–4 28,000 0.4
Wood–Dry 3900 3
Overlay Adhesives
Overlay materials must have good mechanical contact
with the sensing PCB. This is achieved using a
nonconductive adhesive film. This film increases the
Table 3 lists the recommended maximum overlay sensitivity of the system by eliminating any air gaps
between overlay and the sensor pads. 3M™ makes a high
thicknesses for PSoC CapSense applications (plastic
overlay). As stated previously, the dielectric constant plays performance acrylic adhesive called 200MP that is widely
a role in the guideline for maximum thickness of the used in CapSense applications in the form of adhesive
overlay. Common glass has a dielectric constant around εr transfer tape (product numbers 467MP and 468MP).
= 8, while plastic is around εr = 2.5. The ratio of εr/2.5 is an
CapSense Operation with a Gloved Hand
estimate of the overlay thickness relative to plastic for the
same level of sensitivity. Using this rule of thumb, a
If the sensors must work with a gloved hand, add the
common glass overlay is about three times as thick as a
thickness of the glove material to the total overlay stack up
plastic overlay for the same sensitivity.
when sizing the buttons. Dry leather and rubber are similar
to plastic with a dielectric constant of 2.5–3.5. Ski gloves
have a dielectric constant of two or less, depending on the
air content of the glove’s thermal insulation.
January 11, 2008 Document No. 001-41439 Rev. *A 8
[+] Feedback

9. AN2292
Summary About the Author
Name:
Capacitive sensing may take multiple design revisions to Mark Lee
find the best layout for the application. However,
Title: Principal Applications Engineer
knowledge of what has worked in the past and an
understanding of the physics at work reduces design Background: PhD, University of Washington
revisions and accelerates design time. Electrical Engineering, 1992
Contact: olr@cypress.com
In March of 2007, Cypress recataloged all of its application notes using a new documentation number and revision code. This new documentation
number and revision code (001-xxxxx, beginning with rev. **), located in the footer of the document, will be used in all subsequent revisions.
PSoC is a registered trademark of Cypress Semiconductor Corp. quot;Programmable System-on-Chip,quot; PSoC Designer, and PSoC Express are trademarks
of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein may be the property of their respective owners.
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone: 408-943-2600
Fax: 408-943-4730
http://www.cypress.com/
© Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor
Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any
license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or
safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The
inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies
Cypress against all charges.
This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide
patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a
personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative
works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source
Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the
right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or
use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
January 11, 2008 Document No. 001-41439 Rev. *A 9
[+] Feedback