Modeling more complicated logic using sequential statements Skills gained: 1- Identify sequential environment in VHDL 2- Model simple sequential logic This is part of VHDL 360 course

1. VHDL 360© by: Mohamed Samy Samer El-Saadany

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3. Objective Modeling more complicated logic using sequential statements Skills gained: Identify sequential environment in VHDL Model simple sequential logic VHDL 360 © 3

4. Outline Process Description Data Objects Sequential Statements Case Statement IF Statement VHDL 360 © 4

5. Statements VHDL has concurrent statements and sequential statements Concurrent statements are executed in parallel with respect to each other, we explained some of them in Module 1* Sequential statements are executed in sequence with respect to each other. Sequential statements should be written inside a “process” VHDL 360 © 5 Module 1: Create your first model for a simple logic circuit

6. Process Description Process ( <sensitivity_list> ) -- process declarations begin -- process body endprocess; 6 VHDL 360 © Syntax: Process declarations: defines variables, subprograms…etc to be used in process body Process body: defines implementation details of input/output relationship in a sequential manner <sensitivity_list>: List of signals/ports that cause the process to be executed whenever there is a change in their values Example 1: Architecture behave of example1 is Begin process(x,y)-- Every time "x" or "y" value is changed, the process will be executed begin myOutput<= x nand y; endprocess; End behave ;

7. Sequential Assignments Statements inside a “process” are read sequentially and executed when the “process” suspends Signal assignment statement like “F <= A” causes a transaction to be scheduled This means; the current value of A is read and scheduled to drive F when the process suspends. “Process” suspends in two situations When “end process” is reached When a “wait” statement is reached 7 VHDL 360 © Example 2: process(...)-- Assume that initially A = '1' while G, F, Z and X = 'U' Begin Z <= A;-- Signal assignment, schedule a change/transaction, -- however the value of Z still equals 'U' G <='1'; F <= G;-- G is not yet updated, so F is assigned the old value of G X <= F;-- Similarly, X is assigned the old value of F G <='0';-- overrides the previous scheduled transaction, -- however the value of G still equals 'U' Z <= G; endprocess;-- Process suspends => Signals update with scheduled transactions -- G = '0', F = 'U', Z = 'U', X = 'U'

8. Sequential Assignments 8 VHDL 360 © Example 3: Architecture behave offulladderis signal temp :std_logic; Begin process(In1, In2, CarryIn) begin temp <= In1 XOR In2; Sum <= temp XORCarryIn; CarryOut<= (In1 AND In2) OR (CarryInAND temp); endprocess; End behave ; There’s a problem here!

9. Data Objects 9 VHDL 360 © VHDL offers different data objects: Constants Used to store values that can’t be changed during simulation time Signals Used to model connections Signals can be External (Ports) used as an interface for the entity to the outside world (Declared in Entity) Internal used inside the architecture to connect different logic parts (Usually declared in architecture) Assigned using “<=” Outside a process, its value is updated when their signal assignment is executed. Inside a process, its value is updated after the process suspends Variables Used for computations Variables are declared inside a process or sub-programs Assigned using “:=” Value is updated immediately Constant Declaration constant <con_name>: <con_type>; Signal Declaration signal <sig_name>: <sig_type>; Variable Declaration variable <var_name>: <var_type>;

10. Objects Scope 10 VHDL 360 © Each object in VHDL has a scope following the below rules: Objects declared in package are available to all units using that package Objects declared in an entity are available to all architectures of that entity Objects declared in an architecture are available to all statements in that architecture Objects declared in a process are available only within that process Entity architecture1 architecture2 process1 architecture3 process2

11. Data Objects Example 11 VHDL 360 © architecturebehavofmydutis -- Signals scope is the whole architecture signal x, y :std_logic:= 'U';-- Initialization (Not an assignment) signalsigbus:std_logic_vector(7downto0):="01011110"; begin process()-- No sensitivity list, Is this a problem? -- Variables are declared inside a process -- Variables scope is limited to the process variable z :std_logic:= '1'; variablevarbus:std_logic_vector(3downto0):="0001"; begin x <= '1';-- Signal assignment, schedule a change, -- however the value of x still equals 'U' sigbus<="00110101"; z := '1';-- Variable assignment takes effect immediately varbus:="1101"; sigbus(3downto0)<=varbusand"1010";-- overrides the previous scheduled change, -- however sigbus still equals "01011110" x <= z and '0'; z := '0'; y <= z xor '0'; endprocess;-- Process suspends => x = '0', y = '0' and sigbus = "00111000" endarchitecture;

16. Sequential Statements Now let’s introduce sequential statements Case statement If statement loop statements Wait statement Think Hardware VHDL 360 © 16

19. Exercise 1 19 VHDL 360 © a F 2 4 The below code is 2x4 Decoder; Complete it by doing the following: Declare F as an output port Add necessary signals to sensitivity list Add Case statement with all needed branches to create a 2x4 decoder libraryIEEE; useIEEE.std_logic_1164.all; entity decoder2x4 is port(a:instd_logic_vector(1downto0); -- Declare F as an output port <here> ); endentity; Architecture behave of decoder2x4 is Begin process(<here>)-- Add necessary signals to sensitivity list begin -- Add Case statement with all needed branches to create a 2x4 decoder <here> endprocess; EndArchitecture;

20. Sequential Statements Sequential Statements Case statement If statement loop statements Wait statement Think Hardware VHDL 360 © 20

22. Exercise 2 The below code is D Flip-flop with synchronous reset; Complete it by doing the following: Add necessary signals to sensitivity list Add necessary condition to model the rising edge of the clock Add nested If statement to model the synchronous reset 22 VHDL 360 © Libraryieee; useieee.std_logic_1164.all; Entityd_ffis Port( d,clk,rst:instd_logic; Q,nQ:outstd_logic); endentity; Architecturebehavofd_ffis signalQ_int:std_logic; Begin process(...) -- Add necessary signals to sensitivity list begin If(...)then-- Add necessary condition for a rising edge clock ... -- Add a nested If statement to model the synchronous reset endif; endprocess; Q <=Q_int; nQ<=not (Q_int); endbehav;

23. IF Statement 23 VHDL 360 © Example 6: LIBRARYieee; USEieee.std_logic_1164.all; USEieee.std_logic_arith.all; ENTITYadd_subIS port(a, b :ininteger; result :outinteger; operation:instd_logic);-- add or subtract ENDENTITYadd_sub; ARCHITECTURE behave OFadd_subIS BEGIN process(a, b, operation) begin if(operation = '1')then -- Add when operation = '1' result <= a + b; else-- Subtract otherwise result <= a - b; endif; endprocess; ENDARCHITECTURE behave;

24. Exercise 3 The below code is a simple comparator; Complete it by doing the following: Declare 2 bits output port called “result” Add necessary conditions to model “equal to” and “greater than” Comparisons Add another “elsif” branch for “smaller than” comparison 24 VHDL 360 © LIBRARYieee; USEieee.std_logic_1164.all; USEieee.std_logic_unsigned.all; ENTITY comparator IS port(a, b:instd_logic_vector(7downto0); -- Declare a 2 bits output port called "result“ ); ENDENTITY; ARCHITECTURE behave OF comparator IS BEGIN process(a, b) begin if(...)then-- equality result <="00"; elsif(...)then-- greater than result <="01"; ...-- Add another "elsif" branch for "smaller than" comparison else-- covers other cases result <="11"; endif; endprocess; ENDARCHITECTURE;

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