5. Processor count predicted to increase dramatically Source: ITRS 2006 Update DPE: Data Processing Engine
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9. Observation: New Embedded Software Development Tools needed (especially for multicore) Phase 1: simulate platforms at speed for OS porting, driver and application development - virtual platforms Virtual platform: multicore simulation, user modeling, model library Phase 2: next generation functionality built on simulation base – verification solutions for software development - new products from new companies Verification, Debug & Analysis The current market is here The Four Steps to the MP Epiphany™ Adoption over time Abstraction and Efficiency Phase 3: manage/deliver application software for heterogeneous platforms Workbench Phase 4: better programming paradigms and tools to address parallel programming and multicore platform issues Programming Model, Tools, Automation
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16. Virtual Platforms (OVP) are the foundation for the next generation of [embedded] software development environments – especially for multicore Page Phase 1: simulate platforms at speed for OS porting, driver and application development - Open Virtual Platforms Virtual platform: multicore simulation, user modeling, model library Phase 2: next generation functionality built on simulation base – verification solutions for software development - new products from new companies Verification, Debug & Analysis OVP fulfils this need The Four Steps to the MP Epiphany™ Adoption over time Abstraction and Efficiency Phase 3: manage/deliver application software for heterogeneous platforms Workbench Phase 4: better programming paradigms and tools to address parallel programming and multicore platform issues Programming Model, Tools, Automation
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19. Components of OVP Processor Models Page Decode Disassemble Debug IF TLB L1/L2 Cache Extension / SemiHosting / Instrumentation Libraries Decode instruction from memory High Performance Model TLB / MMU Add processor independent I/O support Add instrumentation into application (no overhead) Exceptions Asynchronous Events Behavior L1 Cache Instruction Behavior and Disassembly Standard interface to Debugger (RSP) Processor State Shared Resource Model cache (MMC) Create and manage resources (eg Registers) shared between multiple processor instances Exception Modeling Asynchronous External Events => complete, proven technology and methodology – write your own, or use ours…
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22. Modeling Processors using OVP - some performance numbers for OVP CPUs OVP CPU Models Required Speed OVPsim solution: Ready for next generation application software development! RTL Hardware Verification Hardware / Software Co-Verification Transaction Level Verification (SystemC) Driver Development Firmware Development Application Software Development 10 KHz 100 KHz 1 MIPS 10 MIPS 100 MIPS 1 GIPS 1 KHz
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26. OVPsim Demo Single Processor – Fibonacci series Platform Source (C compiled on X86 Windows) OVPsim run log (runs easily and very fast on normal Windows PC) Application Source (C cross-compiled for target processor)
27. OVPsim Demo Single Processor - Peakspeed Shows maximum speed – depends on application and platform – 1,000 MIPS possible on desktop… Example of peakspeed - Simple contrived example application - Demonstrates maximum speed
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29. OVPsim Demo multicore2 – 2 X MIPS32 2 processors in platform Easy to see instructions per processor and cumulative - No slow down with sharing resources! other processor is reader add buses & connect add memory connect memories to buses one processor is writer
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31. OVPsim Demo manycore24 – 24 X ARM Easy to see instructions per processor and cumulative - no slow down with more processors! - simulate easily 2048 processors, and more… Easy to create platforms of many processors Easy to load software onto many processors
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34. OVPsim Demo Tensilica Integration 2X Diamond Cores Simulation runs easily Encapsulated Models are instanced easily like native OVP models OVP includes processor to processor communication using FIFOs Software on processor 1 is reader Software on processor 2 is writer
35. OVP enables debugging with GDB attached to one processor OVPsim platform waits for GDB debugger connection on standard network socket GDB target remote command connects GDB to OVPsim processor Once connected GDB enables full source level debugging of simulated application Processor to debug in OVPsim platform is nominated as part of icmNewProcessor() Port for GDB connection is specified in icmInit() - zero means use any free port
36. Debugging with Eclipse is easy using CDT encapsulation Eclipse enables graphical source-level debug of OVPsim simulated application – Platform and debugger launched with two mouse clicks Low-level processor state can also be inspected and controlled Eclipse connects to OVPsim through GDB using GDB’s remote serial protocol
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38. OVPsim Demo running simple OS - uClinux OVPsim console starts up - and then awaits a telnet session - When session finished it exits with information Use hyperTerminal to connect to UART in platform - When type in terminal – interact with OS running on simulated processor
39. OVPsim booting uClinux on ARM Atmel AT91sam7 ARM7TDMI 16-Mbit Flash Memory AIC Watchdog Power Saving Chip Id Parallel IO Controller USART USART SRAM ASB Timer Counter Terminal Keyboard interrupts Boot uClinux
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41. OVPsim booting Linux on ARM Integrator / ARM926 Keyboard / Mouse Boot Linux ARM920T Flash LCD Controller Keyboard/Mouse SSRAM SDRAM config regs LED RTC MMC Interface UART GPIO PIC PIC AHB Decoder UART
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45. OVPsim Heterogeneous Platform ARM Nucleus / MIPS Linux ARM920T Flash LCD Controller Keyboard/Mouse SSRAM SDRAM config regs LED RTC MMC Interface UART GPIO PIC PIC AHB Decoder UART Mouse Keyboard UART (TTY2) (16450) UART (TTY1) (SuperIO) UART (TTY0) (SuperIO) Memory (RAM) Malta FPGA KbControl (SuperIO) VGA PIIX4 (Base) USB (PIIX4) PM (PIIX4) IntControl (PIIX4) IDE PCI BUS PCI IACK SysControl (GT64120) LOCAL BUS RTC (PIIX4) Timer (PIIX4) PCI Config Dynamic Bus Connection br br Run Platform Memory (RAM) telnet localhost 9999 MIPS32 34Kc
51. FAST SIMULATION, FREE MODELS, EASY TO USE http://www.ovpworld.org Enabling the next generation of embedded [MultiCore] Software Development
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Notas del editor
Ok, when will your design be in production, Mr. customer? Give me a number of processors please? Bring up Eclipse Let the user choose a number of processors Show how we kick of simulations from 4 processors to the number the customers chose show how well we scale (see next slide)
HW virtual platforms are like TLM, have sense of bus. SW virtual platforms have programmers view, no bus.
HW virtual platforms are like TLM, have sense of bus. SW virtual platforms have programmers view, no bus.
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