2. Contents Introduction and History of gate stack design Moore’s law and transistor development Gate oxide issues and High-k materials Poly-Si replacement and Gate stack processing issues Present gate stack design and future development Summary References and useful websites Questions/Comments.... Oreoluwa Odubela (200364760)
3. Introduction Basic CMOS Transistor The gate dielectric is at the heart of every MOS transistor device. MOS capacitors supply charge that switch the transistor on and off. To maintain/ improve the switching frequency as transistors shrink a smaller channel must carry the same amount of drive current IC manufacturers increase capacitance by making the dielectric thinner. Oreoluwa Odubela (200364760)
4. More Moore’s Law! Moore’s law [1] Transistor Development (1971-2015) Oreoluwa Odubela (200364760) *** Leakage current limited further scaling.
12. Gate Oxide issues and High K Material Reasons for Scaling: W=width of the channel , L=channel length µ=channel carrier mobility , Vg=gate voltage COX =capacitance density associated with gate dielectric when the underlying channel is in the inverted state Vd=drain voltage , Vt=threshold voltage
23. Gate Oxide issues and High K Material Seeking new materials to drive Moore‘s Law Power -industry recognizes that high--k is needed!
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25. Gate Oxide issues and High K Material High k Material and it advantage Benefit of using High k material compared with previous technology
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27. Without a new dielectric material with increased thickness and a higher K value, Moore’s Law would inevitably hit a wall.
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29. The power and heat issue is huge and industry has been searching for solutions for a long time. Intel has solved a major part of the problem by integrating new materials into transistors.
30. Intel has achieved world record performance at dramatically reduced leakage with its new transistor .
50. Future Development According to Moore’ law we should see a trend in transistor development as such: High-k metal gate structures will be more prevalent than Si02 There may be a move from planar CMOS to the use of tri-gate (Intel) and FinFET (AMD, IBM, Motorola) transistors Oreoluwa Odubela (200364760)
54. Seminar on High K Dielectric Solution for MOSFET scaling Final Report by GECKozhikkode
55. Challenges in gate stack engineering by Robert W. Murto, Mark I. Gardner, George A. Brown, Peter M. Zeitzoff, Howard R. Huff, International Sematech, Austin, Texas