1. Dimensioning Space of a Parallel Tuned Amplifier
S. Hietakangas1 ∗ , T. Rahkonen1
1
Department of Electrical and Information Engineering and Infotech Oulu
Electronics Laboratory, University of Oulu
PL 4500, 90014 OULUN YLIOPISTO (Oulu), FINLAND
Tel: +358 8 553 2675 Fax: +358 8 553 2700 e-mail: sih@ee.oulu.fi
Abstract—The purpose of this paper is to study the entire The purpose of ������������ is to prevent the supply from short circuit
dimensioning space of a parallel-tuned integrated circuit that was and to insert a notch to a pre-selected frequency to improve
designed and implemented earlier. The main parameters were stability at that particular frequency. The latter feature is not
swept while keeping the remaining component values fixed, and
performance contours were derived. The main finding was that discussed further here. The size of the capacitor ������������ is fixed
the traditional sweeps of resistively damped switching amplifiers by area limitations and is taken into account at the equations,
match poorly if the resonator ������ value is low - instead, the effect so that one can test different capacitor sizes and evaluate the
of external impedance matching circuit is very significant. impact on the operation of the circuit.
I. I NTRODUCTION
Switching power amplifiers such as class E [1], [2] and
its dual circuit, inverse class E [3], [4] are in the center of
interest both in academia and industry due to their low loss
1
operation. Further, tuned modes of operation such as class C, RFC p p
discussed for example in [5] and also modes in between tuned
and switching modes such as C-E [6] have been analyzed over
the years. cc
s
The drawback of the ideal class E amplifier mentioned first
is the rather high drain peak voltage, whereas the inverse
class E tries to decrese the voltage peak with a different, dual
circuit approach. The circuit topology in this paper is related Fig. 1. Analysed resonator structure
to the implemented amplifier in [7], where a modification
to inverse class E topology was done by setting the DC-
block capacitor into a different place and by the removal A. Admittances in the load network
of series inductive component between the transistor and
The admittance of the output capacitance and RF choke
the resonator at the output. The analysis of this topology
when normalized to load is
together with transistor output capacitance, bias inductance ( )
and both with and without the effects of matching is inspired ������1 ������
= ������ ������������1 ������ − = ������������, (1)
by the work of M. Kazimierczuk [6]. First we will familiarize ������������ ������������������������ ������
ourselves with the analysis and equations of the circuit and
where ������������ is the admittance of the load. Similarly, the admit-
then study the performance of the circuit with and without
tance of the parallel resonator is
matching. In the later sections the effect of parasitics on the
( )
circuit performance is evaluated and simulated loadlines of ������������ ������
= ������ ������������������ ������ − = ������������. (2)
the implemented amplifier are shown to demonstrate the near ������������ ������������������
switching operation of the circuit.
The admittance of the DC-block is
II. A NALYSIS OF PARALLEL RESONATORS ������������
= ������������������������ ������ = ������������. (3)
The resonator structure analyzed is shown in Fig. 1. The ������������
amount of reactances is initially kept at five elements to
Now the combined admittance of (2) and (3) is
avoid too complicated analysis. The capacitor ������1 is the output
capacitance of the transistor which is assumed to be linear in ������������������ ������������ ������������ −������������
= = . (4)
the analysis. In parallel to the capacitor is the ideal supply RF ������������ ������������ (������������ + ������������ ) ������(������ + ������)
choke ������������������ ������ , which is kept large. Together, the ������1 and ������������������ ������
form one of the two parallel resonators. The second and main Now the total admittance of the circuit is simply
parallel resonator is the capacitor ������������ and inductor ������������ that can ������������������������ ������1 ������������������ ������������
= + + . (5)
be tuned close to resonant frequency as in inverse class E. ������������ ������������ ������������ ������������
978-1-4244-8971-8/10$26.00 c 2010 IEEE

2. (5) can be written in a normalized manner III. P ERFORMANCE OF THE CIRCUIT
������������ Similar to [6], the performance of the topology was eval-
������������������������ ������ = 1 + ������������ − . (6) uated by sweeping parameters b and K that control the
������(������ + ������)
size of output capacitance ������1 according to (14) and center
From (6) we can solve the load resistance of the circuit frequency of the main resonator as shown in (9), respectively.
To do this, other parameters were fixed to avoid variation
√ ( )2 of load resistance ������ and to make possible a comparison to
������������
������ = ∣������������������������∣ 12 + ������ + , (7) the implemented and measured amplifier. Equation (7) is not
(������ + ������) used for calculations here, but is shown for the completeness
of design equations. The fixed values in this study are: ������ =
where ������������������������ is the input impedance of the whole circuit. By
1.04552, ������ = 4, ������������ = 0.77, ������������������ ������ = 5e-6, supply voltage ������������������
keeping ������������������������ fixed one can calculate the necessary ������ that
= 5.5 V and operational frequency ������ = 1.6 GHz. Instead of a
keeps the drain voltage swing constant. If we want to calculate
complete transistor model, I-V function was implemented by
the components in the main resonant circuit, the resonant
a voltage controlled current source. Kazimierczuk used time-
frequency of the resonator has to be solved. This can be
domain state model analysis, which could be applied here,
done with the help of (2) and the fact that quality factors
too. However, it can handle only lumped components and
of components ������������ and ������������ are
inherently assumes zero distance between the components. To
������ cope with the distributed effects, harmonic balance (HB) has
������������ = ������0 ������������ ������ = , (8) been used here, instead. This evaluation is relatively simple
������0 ������������
to perform in a commercial HB simulator as it has been done
respectively, where the ������0 is the resonant frequency of the here.
main parallel resonator. Now the component values in (2) can
A. Performance with broadband resistive load
be substituted with quality factors from (8) and we get
( ) The Fig. 2 below shows the fundamental output power and
������ ������0 drain efficiency as a function of ������ and ������. The figure shows
������ = ������������ − . (9)
������0 ������ a relatively narrow peak efficiency and power zone when ������
is -0.4 to -0.5 together with ������ which is from 0.4 to 2.0. Peak
To be able to calculate the values of ������������ and ������������ , ������0 has to be power 4.648 W occurs at one point, where ������ is 1 and ������ is
solved. After some manipulation we get -0.65. Peak efficiency has two maximum points at ������ = 0.95, ������
√( ) = -0.55 and ������ = 1.175 ������ = -0.6 both of which have the same
2
������������ maxima 77.16 %. Even though the peak efficiency and peak
+ 4������ 2
������������ ������������ power do not meet at the same point, the output power is over
������0 = + . (10)
−2������������ 2 4.1 W at at all times when the drain efficiency is over 76 %
according to the Fig. 2. In all, the curves in Fig. 2 represent a
B. Component calculation traditional class B operation with no additional pulse shaping
Now we have all the necessary variables to calculate com- in the simulated circuit.
ponent values for a certain ������, ������, ������, impedance level ������������������������ , 3.1
50 2.1
supply choke ������������������ ������ , quality factor ������������ and center frequency
������. −0.2
35
First one has to solve resistive load ������ from (7), then the 4.1 65
center frequency ������0 of the main parallel resonator from (10). −0.4 76
3.
76 4.1 501
K
Then one can calculate all components from equations below: 77
−0.6 77 65
65 76
������ 4.1
50
3.1
76 4.1
������������ = , (11) 35
2.1 65
4.1
50
������0 ������������ −0.8
5
20
1.1 3.1
35
2.1
20
1.1
5 5
0.1 0.1
������������ 0 0.5 1 1.5 2 2.5
������������ = , (12) b
������0 ������
Fig. 2. Efficiency and power of ideal circuit
������
������������ = , (13)
������������
B. Performance with ideal low pass and high pass matching
and Since the quality factor of the analysed circuit was rather
������ 1 low due to limited chip area, the effect of classic, single L-
������1 = + . (14)
������������ ������ 2 ������������������ ������ type matching network having a ������ of 3.4 to the operation

3. of the circuit became a point of interest. This type of 50 the L-circuit used above, but a transmission line accompanied
Ω matching was designed for simulation purposes. The first with a capacitor to ground in the middle. To check the
series reactance of the low and high pass match is ������������������ = effects of both of these, the on-chip resonator and the off-
14.74 Ω and parallel reactance after that (when looking from chip matching network were modelled by S-parameter file
the power amplifier to the load) is ������������������ = 13.56 Ω. obtained from EM-simulator and measurements, respectively.
Fig. 3 shows the efficiency and power of the circuit sweeps The S-parameters from the EM-simulated resonator were used
obtained with a single L-type low pass matching. It becomes to derive a discrete resonator with five additional parasitics
shown in Fig. 4. The additional parasitics are: ������������������ = 0.1 nH,
55 3
2.65 1.6
75
3.6
−0.2
45 25
75 65 2.1
4.1
in in
4.1 3.1
−0.4
4.6 55 2.35
6
75 3.6
K
4.6 5.1 65 45 LS s
−0.6 5.1 3.1 LP
65 75 4.1
55 4.6 75 3.6 55
3.6 4.1
45
3.1 4.6 65
35
2.6
2.1 65 75 4.6
55 4.1 4.1
75 p p
25
1.6 3.6
45
3.1
35 65 4.1
−0.8 5 15
1.1 2.6
2.1
25 55
3.6
45
1.6
15
1.1 3.1
35
2.6
2.1
25
1.6
0.6 0.6 5 15
1.1
5 0.6 5
0.1 0.1 0.1
s
0 0.5 1 1.5 2 2.5
b
Fig. 3. Efficiency and power of low pass matched circuit
Fig. 4. Resonator with five parasitics
immediately clear that the region of good operation has
spread to different area than in Fig. 2, but at the same time ������������������ = 0.1 Ω, ������������������ = 0.15 Ω, ������������ = 0.39 nH and ������������������ = 0.15
the maximum efficiency and power have increased in value. Ω. This discrete approximation still enables the sweeps of the
Maximum achievable efficiency has increased to 81.21 % at parameters ������ and ������. The results of the sweeps are shown in
������ = -0.5 and ������ = 0.625 while the fundamental output power Fig. 5. The peak efficiency and power areas in the figure have
has the value of 4.925 W. The maximum power, 5.364 W
5
is achieved at ������ = -0.55 and ������ = 0.5 while efficiency at 0.6
15
0.6
1.1
1.1
that point is 76.42 %. The common feature here is the fact 5 15
2.1
1 2 15
that both of the peaks are achieved when the transistor output
25 1.6
1.6
653.1
653.1.6
capacitance is nearly half of the original size. The peak power 1.1
3.61
1.1
3 4.
35
and efficiency are reached at a slightly different ������ and ������
K
0
45
2.6
256
1.
3.1
values, which means that some compromise has to be made 55 2.1
2.15
65 2.6 35 2.1
45
5
15
6
in the choice of design values. The higher ������ matching seems
2.
211 3
4.2 2.1
3. .
−1 125.66 .6
15 1.6
to change the performance of the circuit and at the same time
15
0.6
3. 55
adds restrictions to the size of the transistor. Also, the higher ������ 1
2.6
35
seems to dominate the operation of the circuit since the highest 0 0.5 1 1.5 2 2.5
efficiency and power is achieved in a somewhat narrower area. b
In the case of high pass matching, the efficiency and power Fig. 5. Efficiency and power of circuit with measured match
form the curves of the same kind as the low pass matching.
The only difference is that the area, where the power peaks, widened to a much broader area, especially in terms of design
is somewhat smaller. Otherwise, the curves looked identical value ������. Maximum efficiency has two peaks to consider: 70.1
and therefore the curves are not shown here. However, some % at ������ = 0.25 and ������ = 0 with the output power of 3.76 W and
numbers can be told: The highest efficiency 80.37 % is 73.94 % at ������ = -0.05 and ������ = 0.1 with output power of 3.51
achieved at ������ = -0.5 and ������ = 0.667 while maximum power W. The latter is more realizable since it does not require the
is 4.761 W. The highest power, 5.205 W is at the case when ������1 to be resonated away with ������������������ ������ . Maximum power has
������ = -0.55 and ������ = 0.5 while efficiency is 75.16 %. The peak two peaks: 4.55 W at ������ = 0.6 and ������ = 0 with the efficiency
power and efficiency points are almost identical between the of 62.86 % and 4.858 W at ������ = 0.45 and ������ = 0.125 with the
two matching approaches. Also with high pass matching, some efficiency of 68.53 %. The latter is again more realizable in
compromises have to be made in terms of efficiency and power terms of design values.
when the design parameters are chosen. When we compare the simulation results from the amplifier
designed in [7], output power was about 3.4 W and efficiency
C. Performance comparison with added parasitics around 70 %. If we approximate the value of the parameter ������
The layout implementation of ������������ , ������������ and ������������ generate from EM simulations and ������ of the transistor from the loadlines
some parasitics. Also, the impedance matching used is not (assuming that the output capacitance is linear), we get roughly

4. -0.286 and 0.1447, respectively. Now the efficiency and output power dissipation. The loadlines therefore show how well the
power of the analysis in this subsection, with ������ = -0.3 transistors perform as a switch.
and ������ = 0.15 are 70.96 % and 2.72 W, respectively. The
IV. S UMMARY
efficiency seems to be a perfect match, but the simulated
output power is approximately 20 % smaller than in the This paper analysed a load normalised parallel circuit and
simulations of the reference design. This discrepancy in power swept two circuit parameters to study the values of both
might be caused by the slight load mismatch of simulated the maximum efficiency and the output power of the circuit.
and measured matching circuits, 4.7 Ω vs. 5.4 Ω, respectively. Traditionally, the analysis of switching amplifiers has used
Also, the performance of the main parallel resonator proved only the components of the resonators, not so much the bias,
to be rather sensitive to both resistive and reactive mismatch, matching nor the distances between the components as it is
which underlines both the importance of matching and the done here. The approach in [6] has limitations in terms of
difficulty of implementing well performing matching at low distributed components and this is avoided in this work by
impedances. the use of HB simulations. The parasitics, the Q-value of
Compared with measurement results from [7] neither the load matching and distributed nature of wide, high current
simulations done in that work nor the approach here can transistors has to be carefully taken into account since all of
explain the initially measured low output power, about 0.9 W them can be detrimental to the performance of the amplifier.
achieved without any further tuning to the implemented am- However, the simulation procedure studied here, with only
plifier. However, the procedure here seems to match relatively couple parasitics added to the simple resonator, is found
well with simulations done with the implemented amplifier to match relatively well with previous results achieved with
using foundry components. foundry components. The found values work as base values for
further simulations of to be designed tuned/switching power
D. Loadlines and approximation of output capacitance amplifier. Further, the small changes in load reactance and
One reason for the found discrepancy between measured resistance of the matching network is found to have great
and simulated results can be found in the distributed structure influence over the performance of the resonating circuit and
of the transistor itself. The transistor is physically large and therefore great care has to be taken in the design and im-
its different portions operate in different modes, as seen in plementation of accurate matching at the used low impedance
Fig. 6, which shows the simulated loadlines of three transistors levels. The loadlines of the drain current and voltage reveal the
located at the very ends and in the center of a tuned amplifier. switch-like operation of the circuit designed, regardless of the
This transistor is used and implemented in [7]. The loadlines fact that the series inductance of the inverse class E amplifier
was not implemented and the low ������ of the resonator which
leave the pulse shaping only partial.
0.25 V. ACKNOWLEDGMENT
0.2 This work has been supported by The Academy of Finland,
0.15 Infotech Oulu Graduate School, TriQuint Semiconductor Inc.,
Id, A
Nokia Foundation, Tauno T¨ nning Foundation, Ulla Tuominen
o
0.1
Foundation and The foundation of Riitta and Jorma J. Takanen.
0.05
R EFERENCES
0
[1] N. O. Sokal and A. D. Sokal, “Class e-a new class of high-efficiency
tuned single-ended switching power amplifiers,” IEEE Journal of Solid-
0 2 4 6 8 10 12 14
Vd, V State Circuits, vol. 10, no. 3, pp. 168–176, Jun 1975.
[2] F. Raab, “Idealized operation of the class e tuned power amplifier,”
Circuits and Systems, IEEE Transactions on, vol. 24, no. 12, pp. 725–735,
Fig. 6. Loadline curves of 3 parallel transistors Dec 1977.
[3] T. Mury and V. Fusco, “Series-l/parallel-tuned class-e power amplifier
analysis,” in Proc. European Microwave Conference, vol. 1, 2005, pp. 4
are obtained by taking the simulated drain current and subtract- pp.–.
ing a proper ������1 ������������ term which eliminates any negative swings
������������ [4] ——, “Analysis of the effect of finite d.c. blocking capacitance and finite
of both drain current and dissipated power. The approximated d.c. feed inductance on the performance of inverse class-e amplifiers,”
IEE Proceedings -Circuits, Devices and Systems, vol. 153, no. 2, pp.
output capacitance value ������1 has been used in the section III-C. 129–135, 2006.
Dots in the Fig. 6 are equally timed points of one cycle. The [5] H. L. Krauss, C. W. Bostian, and F. H. Raab, Solid State Radio
three dots reveal the differences of phase of the one cycle. Engineering. John Wiley & Sons, 1980.
[6] M. Kazimierczuk and W. Tabisz, “Class c-e high-efficiency tuned power
All transistors are rotating towards peak voltage from the amplifier,” Circuits and Systems, IEEE Transactions on, vol. 36, no. 3,
continuous drain current phase (transistor closed). According pp. 421–428, March 1989.
to the curves, the phase difference of ������������ voltages is 10 − 15 ∘ [7] S. Hietakangas, J. Typp¨ , and T. Rahkonen, “Design of integrated 1.6
o
ghz, 2 w tuned rf power amplifier,” Analog Integrated Circuits and
and all transistors are showing a switch like behaviour. Be- Signal Processing, An International Journal, vol. 64, no. 3, pp. 261–
cause the switching has spread in time, the transistors are 270, September 2010, special Issue on Selected Papers from NORCHIP
partially conducting when voltage is high, hence increasing 2008.