Embedded system board hardware architecture.

1. Introduction to Embedded Systems
Embedded system board
hardware architecture.

2. 1. What is Embedded Systems
• Embedded Systems or Electronics systems that include an application
Specific Integrated Circuit or a Microcontroller to perform a specific
dedicated application.
• Embedded System is pre-programmed to do a specific function while a
general purpose system could be used to run any program of your choice.
Block diagram of a typical embedded system is
shown in fig.

3. 2. Typical embedded board structure
For instance board Embest SBC6000X showed on fig.

4. 3. Microcontroller Core Architecture
We will consider microcontroller core based on most popular architecture
ARM7TDMI.
The ARM7TDMI core is based on the Von Neumann architecture with a 32-
bit data bus that carries both instructions and data. Load, store, and swap
instructions can access data from memory. Data can be 8-bit, 16-bit, and 32-bit.
Operating modes
The ARM7TDMI core has seven modes of operation:
• User mode is the usual program execution state
• Fast Interrupt (FIQ) mode supports data transfer or channel processes to
allow very fast interrupt processing and to preserve values across
interrupt calls
• Interrupt (IRQ) mode is used for general purpose interrupt handling
• Supervisor mode is a protected mode for the operating system
• Abort mode is entered after a data or instruction prefetch abort
• System mode is a privileged user mode for the operating system
• Undefined mode is entered when an undefined instruction is executed

6. Bancked - mean providing multiple copies of a register at the same
address.
LR - R14 register is Link Register for store context return address
SP - R13 register is Stack Pointer
Current Program Status Register (CPSR)
Mode bits - shows which mode is current System, User, Fiq, Irq, Undefined,
Abort
I and F bit - control the enabling and disabling of interrupts
T bit - shows is core in the thumb mode ("1" 16-bit instruction set, "0" 32-bit)

7. 4. Input/Output Ports
The digital signal is waveform that switches between
two voltage levels representing the two states of a Boolean
value (False - "0" and True - "1").
(1) low level mean "0", (2) high level Note: CMOS Vdd can be 1.8; 2.5; 3,3; 5V
mean "1", (3) rising edge, and (4) TTL Vcc is 5V
falling edge.
4.1 What is digital signal?
Technology Low Level
"0 "
High Level
"1"
CMOS 0 V to VDD/2 VDD/2 to VDD
TTL 0 V to 0.8 V 2 V to VCC

8. 4.2 IO port control registers
• Enable/Disable Register - used to connect pin to general
purpose IO port or to embedded peripheral. 0/1 - mean connect/
disconnect
• Output Register - used to control pin level 0/1.
• Input Register - to read pin level 0/1.
• Connect/Disconnect Pull-Up Register - used in case pin is
input to enable/disable pull-up resistor.
Pull-up resistors are used in electronic logic circuits to ensure that inputs to
logic systems settle at expected logic levels if external devices are
disconnected or high-impedance is introduced
• Enable/Disable Open Drain Mode - to enable/disable open
drain(collector) mode
Open drain (collector) mode - give possibility connect external pull-up
resistor to alternative voltage. For instance to get output with digital level 5V on
microcontroller with power supply 3.3V through external pull-up to bus 5V.
• Enable/Disable Interrupt - this feature for pins configured as
input to enable/disable interrupt in case signal level is changed

9. 4.3 Typical IO port application
IO ports can be used as for embedded peripheral
purpose and for control some external loads (output) and
acquire signals from sensors, buttons (input).
Below is showed typical input usage to acquire signal
from button.

10. Output port pin has current limitation refer to electrical
characteristic documentation. Due to current limitation to
avoid port destruction additional external transistor should
be used to switch led.
On the next fig showed how to control led by output pin.

11. 5. Interrupts
There are two types of interrupts available on ARM
processor. The first type is the interrupt
caused by external peripherals (FIQ, IRQ) and the
second type is caused by software SWI assembler
instruction.
External Peripheral interrupt type has two priority
level:
•FIQ - for source that requires fast response time for
example DMA
•IRQ - for general purpose interrupts like periodic
timers
Note: FIQ interrupts have the highest priority, if a higher
priority interrupt goes active, the current ISR is interrupted
and the higher-priority ISR is executed.

12. 6. Serial Interfaces
A USART (Universal Synchronous/Asynchronous Receiver/Transmitter) is
serial interface peripheral that facilitates communication through RS-232 or RS-
485 interface. The USART controller based on shift register Tx/Rx. Additional
register used to define clock which specify baud rate.
The baud rate of USART is depend on physical layer, common usage
speed is 1200, 9600, … 115200. Frame format is shown below.
USART module has two pins Rx - to receive data and TX - to transmit.
In case node1 connect to node2 - Rx1 should be crosswise connected to Tx2
and Tx1 to Rx2.
6.1 USART

13. The SPI circuit is a synchronous serial data link that provides
communication with external devices in Master or Slave Mode. It also used for
communication between processors. SPI in comparison with USART is faster
(up to ~50Mbps) and has additional signal line “clock”.
The SPI system consists of two data lines and two control lines:
• Master Out Slave In (MOSI): This data line supplies the output data from
the master shifted into the input(s) of the slave(s).
• Master In Slave Out (MISO): This data line supplies the output data from
a slave to the input of the master.
• Serial Clock (SCK): This control line is driven by the master and regulates
the flow of the data bits. The master may transmit data at a variety of baud
rates.
• Slave Select (SS): This control line allows slaves to be turned on and off
by master.
6.2 SPI (Serial Peripheral Interface)

14. Fig: SPI data time diagram
CPOL 0:1 – set an polarity of clock signals ; CPHA 0:1 – set phase clock
mode
The SPI implementation circuit is showed on fig below. There is one
master device and three slave devices that handled by NPCS0, NPCS1, NPCS3
signals.

15. 6.3 I2C (I-two-C interface)
The I2C interface is a multi-master serial single-ended computer bus
invented by Philips used for attaching low-speed peripherals to embedded
system. Not to be confused with the term Two Wire Interface which only
describes a compatible hardware interface.
The I²C in comparison with SPI is using addressing instead NSS (slave select)
signal. I2C addressing mode can be 7-bit or 10-bit.
The I2C bus support next speed modes:

10kbit/s – Low Mode

100 kbit/s - Standard Mode

400 kbit/s - Fast mode.
The I²C uses only two bidirectional open-drain lines, Serial Data Line (SDA)
and Serial Clock (SCL), pulled up with resistors (about 10kOm). Typical voltages
used are +5 V or +3.3 V.
The address and the data bytes are sent most significant bit first. The start bit
is indicated by a high-to-low transition of SDA with SCL high; the stop bit is
indicated by a low-to-high transition of SDA with SCL high. All other transitions
of SDA take place with SCL low.

16. The I2C transfer sequence next:
The Master is sending a start bit followed by the 7-bit address, the last
address e bit R/W representing whether it wishes to write(0) or read(1) from
the Slave.
The Slave will respond with an ACK bit (active low for acknowledged) for
that address. The master then continues in either transmit or receive mode
(according to the read/write bit it sent), and the Slave continues to receive or
transmit.
R/W – bit define read mode in case level “1” and write mode if “0”.
ACK/NACK – if Slave set in bit ACK “0” that mean acknowledge,
otherwise level “1” mean decline.

17. 7. SRAM and SDRAM what is the
difference?
The SRAM or (Static Random Access Memory) is static type of memory.
It is called “static” because it does not have to be refreshed. SRAM access
times are very fast because it doesn’t need to pause between cycle times. It is
very expensive memory.
The SDRAM or (Synchronous Dynamic Random Access Memory) is a
type of computer storage that needs frequent refreshing and has a
synchronous interface. It is slower than SRAM because it refers to the
microprocessor clock before responding thus synchronizing to the system bus
and requiring a pause between cycles.
Below showed SRAM/SDRAM table comparison:
Attribute SRAM SDRAM
Speed Fast Slower than
SRAM
Price Expensive Chip
Capacity ~4Mbit ~4Gbyte
Power
consumption
Low High(due to
refreshing)

18. 8. NAND and NOR what is the difference?
NOR offers faster read speed and random access capabilities as it has
both Addressing and Data Bus,that making it suitable for execute in place.
From last property NOR flash used for code storage in embedded devices.
Software typically does not have to worry about error correction or bad blocks.
NOR flash is lower density and has lower write speed than NAND flash.
NAND flash is faster but does not support execute in place. Additionally,
bad block management is required for NAND flash as well as complex error
correction. NAND flash is available at much higher densities than NOR flash
and is a lot cheaper.
Below is table comparison:
Attribute NOR NAND
Capacity Up to 16Mbit Up to 4Gbit
Speed Fast Read
Slow Write
Erase Very Slow
Fast Read
Fast Write
Fast Erase
Interface connection Address and Data Bus Data bus combined
with address, toggling
CLE, ALE
Access Random Sequential by blocks