1. SI Design Guide for
DDR2/3 PCB
46

2. 47

3. SI Design Guide for
DDR2/3 PCB
48

4. 49

5. SI Design Guide for
DDR2/3 PCB
50

6. 51

7. SI Design Guide for
DDR2/3 PCB
52

8. 53

9. SI Design Guide for
DDR2/3 PCB
Output Buffer
= Diff. SSTL Class1 8mA (Altera FPGA)
(Output Impedance = 25.7 Ohm)
54

10. VIH=+250mV
VIL=-250mV
55

11. SI Design Guide for
DDR2/3 PCB
473mV
VIH=+250mV
VIL=-250mV
56

12. OUT
PULLUP
PULLDOWN
logic_in
enable
inv_out
V2
0
1
2
W=0.12mm
P=45mm
SP=0.1mm
IN
POWER
GND
OUT
inv_in
IN
POWER
GND
OUT
inv_in
0
0
V+-Name=required
1
2
W=0.12mm
P=5mm
SP=0.1mm
1
2
W=0.12mm
P=5mm
SP=0.1mm
1
2
W=0.12mm
P=10mm
SP=0.1mm
1
2
W=0.12mm
P=10mm
SP=0.1mm
100
R26
V+-Name=required1
VIH=+250mV
VIL=-250mV
57

13. SI Design Guide for
DDR2/3 PCB
58

14. 59

15. SI Design Guide for
DDR2/3 PCB
VIH=1.15V
60

16. 61

17. SI Design Guide for
DDR2/3 PCB
40dB 34dB
498MHz(3rd
Harmonic)
62

18. 63

19. SI Design Guide for
DDR2/3 PCB
Memory Controller
I/O I/O
DDR2 Memory
64

20. 65

21. SI Design Guide for
DDR2/3 PCB
ODT_Disable
ODT_150Ohmn
ODT_75Ohm
ODT_50Ohm
66

22. 67

23. SI Design Guide for
DDR2/3 PCB
TL2 TL1
68

24. 69

25. SI Design Guide for
DDR2/3 PCB
3. DDR2 SI Simulation Guide
70

26. 71

27. SI Design Guide for
DDR2/3 PCB
Memory Controller
(BGA type)
DDR2 Memory
DQ / DM / DQS / Clock
Address / CMD / Ctrl
trace
72

28. 73

29. SI Design Guide for
DDR2/3 PCB
74

30. 75

31. SI Design Guide for
DDR2/3 PCB
76

32. 77

33. SI Design Guide for
DDR2/3 PCB
78

34. 79

35. SI Design Guide for
DDR2/3 PCB
80

36. 81

37. SI Design Guide for
DDR2/3 PCB
82

38. 83

39. SI Design Guide for
DDR2/3 PCB
84

40. 85

41. SI Design Guide for
DDR2/3 PCB
86

42. 87

43. SI Design Guide for
DDR2/3 PCB
88

44. 4. Automatic Verification
89

45. SI Design Guide for
DDR2/3 PCB
90