The computer system has a program counter, memory address register, memory buffer register, and instruction register that work together to fetch and execute instructions. It stores instructions in a 4-bit format and uses registers like the accumulator and sequence register to perform operations. Memory reference instructions include AND, ADD, STO, and branch instructions while register instructions modify the accumulator. Input/output instructions allow skipping on flags or reading/writing from ports. The fetch cycle reads instructions from memory into the instruction register before executing them in the execute cycle.

1. Computer design

2. overview
 System configuration
 Computer instructions
 Execution of instructions

3. System configuration
 Program Counter (PC)
 12 bits
 The address of the next instruction to be stored
 Memory Address Register (MAR)
 12 bits
 Used to address specific memory locations
 The memory is loaded from the PC when an instruction
is read from memory
 Memory Buffer Register (B)
 12 bits
 Instruction Register
 4 bits
 It holds operation code of the current instruction to be
executed

4. System configuration…
 E,F and S flip flops
 1 bit registers
 E – for shifting operation and also to get the carry from
an addition
 F – fetch and execute cycles
 S – start or stop
 Accumulator Register (A)
 That operates on the data previously stored in memory
 Sequence Register (G)
 Generate timing signals upon initiate the micro-
operations
 Input Register (N) and Output Register (U)
 9 bits
 Extra 1 bit is a flag bit

5. Computer instructions
Data format(arithmetic)
sign 1 1 1 1 11 1 9 8 7 6 5 4 3 2 1
5 4 3 2 0
 Data format(logical operand)
1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1
6 5 4 3 2 1 0
 Data format(input/output data)
Character1 Character 2

6. Computer instructions
Instruction format
Memory reference instruction
operation Address
Register – reference instruction
0110 Type of register operation
Input/output instruction
0111 Type of I/O operation

7. Memory reference instruction
Symbol Hexa decimal Description Function
Code
AND 0 m* AND to A A  A AND M
ADD 1m Add to A A A+M, E 
Carry
STO 2m Store in A MA
ISZ 3m Increment and M  M+1
skip if zero
BSB 4m Branch to M PC +5000,
subroutine PC m+1
BUN 5m Branch PCm
unconditionally
* - m is the address part of the instruction, M is the memory word
addressed by m

8. Register reference instruction
Symbol r=q6t3 Hexa decimal Description
Code
CLA rB12 6800 Clear A
CLE rB11 6400 Clear E
CMA rB10 6200 Complement A
CME rB9 6100 Complement E
SHR rB8 6080 Shift right A and
E
SHL rB7 6040 Shift Left A and
E
INC rB6 6020 Increment A
SPA rB5A16 6010 Skip on positive
A
SNA rB4A’16 6008 Skip on
Negative A
SZA rB3Az 6004 Skip on zero A

9. Input-output instructions
Symbol P=q7t3 Hexadecimal Description
Code
SKI PB12N9 7800 Skip on input
flag
INP PB11 7400 Input to A
SKO PB10U9 7200 Skip on output
flag
OUT PB9 7100 Output from A

10. Execution of instructions
 Once S=1,
 An instruction whose address is in PC is read from
memory
 Its operation is transferred to I and PC incremented
by 1 to prepare it for the next instruction
 If instruction is memory reference type, it may be
necessary to access memory again to read an
operand.
 When F=0, the word read from the memory is
executed to be an instruction and the computer is
said to be in an instruction fetch cycle
 When f=1 the word read from memory is taken as
an operand and computer is said to be in a data
execute cycle.

11. Fetch cycle
 F’t0 => MAR  PC, transfer instruction address
 F’t1=> BM, PCPC +1, read instruction,
increment PC
 F’t2=> IB (OP), transfer opcode
 F’(q0+q1+q2+q3+q4).t3 => F 1, go to execute
cycle
 q5.t3 => PCB, branch unconditionally
 q6.t3=> execute register reference instruction
 q7.t3 => execute I/O reference instruction

12. Execute Cycle
 F.t0 => MAR  B, transfer address part
 F.(q0 +q1+q3)t1=> BM, read operand
 F.(t2+t3) => Execute memory reference
instruction
 F.t3 => F 0, return to fetch cycle